3D Memory Word Line Biasing for Programming Time Equalization
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Solution Overview
Problem
In three-dimensional memory devices, signal loading delays occur due to varying access path lengths of word lines, which are exacerbated by increased stacked layers, leading to inconsistent programming times and performance degradation.
Innovation Solution
The semiconductor device employs a bit line unit to divide word line units into proximal and distal segments, with a word line drive unit providing differential bias voltages in charging and discharging phases to equalize programming times across word line subunits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the word line drive unit is arranged in the middle part of the storage area, then the difference between access path lengths is reduced, but the problem of signal loading delay still exists when the number of stacked layers increases
Solution Approach 1:
The bit line unit divides the word line unit into a first word line unit and a second word line unit, creating segmented regions that can be independently controlled. This segmentation allows different bias voltages to be applied to different segments, compensating for the signal loading delay caused by varying access path lengths in multi-layer stacked structures.
Solution Approach 2:
The patent applies different bias voltages (first bias voltage and second bias voltage) to different segments of the bit line unit corresponding to different word line units. This local quality approach ensures that each segment receives customized voltage compensation based on its specific access path characteristics, thereby equalizing programming times across all word lines regardless of their distance from the word line drive unit.
2Quantity of substance
If the number of stacked layers is increased, then the storage capacity is improved, but the difference between access path lengths is increased leading to programming time inconsistency
Solution Approach 1:
By dividing the bit line unit into multiple segments (first bit line unit segment, second bit line unit segment, etc.) that correspond to different word line units, the patent enables independent voltage control for each segment. This segmentation allows precise timing compensation for word lines at different distances, ensuring consistent programming times even as the number of stacked layers increases to boost storage capacity.
Solution Approach 2:
The patent changes the voltage parameter by applying different bias voltages (first bias voltage and second bias voltage) to different bit line segments during programming operations. This parameter change compensates for the increased access path length differences caused by more stacked layers, thereby maintaining programming time consistency across all word lines in high-capacity multi-layer structures.
Data Source
AI summary
A semiconductor device includes a plurality of bit line units, a word line unit, a bit line drive unit, and a word line drive unit. The word line unit comprises a plurality of word line stacked in a first direction, and a first and a second word line units in a second direction. A distance between the second word line unit and the word line drive unit is greater than a distance between the first word line unit and the word line drive unit. The word line drive unit provides the word line unit with a driving voltage for programming. The bit line drive unit applies a first bias voltage to a bit line unit corresponding to the first word line unit during a charging phase of programming, and a second bias voltage to a bit line unit corresponding to the second word line unit during a discharging phase.