3D Memory Word-Line Biasing to Prevent Pass Transistor Turn-On
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Solution Overview
Problem
The integration limit of semiconductor devices is reached when forming memory cells in a single layer on a substrate, and there is a need to improve the operational reliability of three-dimensional semiconductor devices.
Innovation Solution
A semiconductor device with a cell array, pass transistors, an operation voltage supplying circuit, and a well bias supplying circuit is designed to manage voltages and well biases during read, program, and erase operations, including applying specific well biases to prevent abnormal turn-on of pass transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked in three dimensions to improve integration, then the degree of integration is improved, but the operational reliability deteriorates due to voltage instability during discharge periods
Solution Approach 1:
The patent applies a negative well bias voltage to the well region of pass transistors during the discharge period of unselected local word lines. This parameter change in the well bias voltage prevents abnormal turn-on of pass transistors caused by voltage drops, thereby maintaining operational reliability while enabling three-dimensional memory cell stacking for improved integration.
2Device complexity
If pass transistors are used to connect global word lines to local word lines, then the device complexity is reduced, but abnormal turn-on occurs during discharge periods due to voltage drops
Solution Approach 1:
The patent applies a negative well bias voltage to the well region of pass transistors before and during the discharge period of unselected local word lines. This preliminary anti-action counteracts the voltage drop that would cause abnormal turn-on of pass transistors, preventing the reliability issue while maintaining the simplified device structure.
3Speed
If unselected local word lines are discharged during read operation, then the read speed is improved, but voltage drops cause abnormal turn-on of pass transistors
Solution Approach 1:
The patent maintains a negative well bias voltage on the well region of pass transistors during the discharge period of unselected local word lines. This parameter change compensates for voltage drops that occur during rapid discharge, preventing abnormal turn-on and ensuring operational reliability while allowing fast read operations.
Data Source
AI summary
A semiconductor device may include: a cell array including memory cells connected to local word lines; pass transistors that connect global word lines and the local word lines in response to a block selection signal; an operation voltage supplying circuit that applies a read voltage or a pass voltage to the global word lines; and a well bias supplying circuit that, during a read operation, applies a well bias having a negative level to a well region of the pass transistor connected to a selected local word line, in a discharge period in which an unselected local word line is discharged.