3D Memory Word-Line Layout for Low Resistance and Block Isolation
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Solution Overview
Problem
Semiconductor devices face challenges in reducing word-line resistance, which affects their performance and integration density, particularly in three-dimensional (3D) memory devices where stacked structures increase complexity and resistance.
Innovation Solution
The implementation of slits and isolation patterns at specific regions of word lines and selection lines to isolate and merge edge portions of word lines, reducing resistance by creating a continuous structure across memory blocks while maintaining independent operation of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word lines are made continuous across memory blocks to reduce resistance, then word-line resistance decreases, but isolation between memory blocks becomes difficult
Solution Approach 1:
The patent divides the word line into multiple segments by introducing slits at specific locations. The word line is segmented into first and second portions that are electrically isolated in the center region but connected at edge regions, allowing resistance reduction while maintaining block isolation.
Solution Approach 2:
The patent applies different structural characteristics to different regions of the word line. The center region features slits for isolation, while edge regions maintain continuity for low resistance. This local differentiation allows simultaneous achievement of isolation and conductivity.
2Device complexity
If slits are introduced to isolate memory blocks, then block isolation improves, but word-line resistance increases
Solution Approach 1:
The patent introduces slits only in the center region of the word line rather than across the entire length. This partial action provides sufficient isolation between memory blocks while preserving word line continuity at edge regions to maintain low resistance.
3Reliability
If edge portions of word lines are merged to reduce resistance, then word-line resistance decreases, but isolation between adjacent memory blocks is compromised
Solution Approach 1:
The patent segments the word line structure into distinct regions with different connectivity characteristics. Edge portions are merged to reduce resistance while center portions are slit to maintain isolation, creating a segmented structure that satisfies both requirements.
Solution Approach 2:
The patent creates an asymmetric structure where the treatment of word line regions differs between center and edge areas. This asymmetric design allows optimization of each region for its specific function: continuity at edges for conductivity, isolation at center for boundary definition.
Data Source
AI summary
A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.