3D Memory Word-Line Voltage Sequencing for Fast Erase Retention
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Solution Overview
Problem
Storage devices with three-dimensional memory cells face challenges in achieving high data retention characteristics and shorter operating times.
Innovation Solution
A storage device design that applies different voltage levels to first and second word lines during distinct time periods to efficiently erase data, utilizing a sequence of weak and strong erasing processes to minimize the threshold voltage of memory cell transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single high-voltage erasing operation is applied to all word lines simultaneously, then data erasure speed is improved, but data retention characteristics deteriorate due to excessive threshold voltage reduction
Solution Approach 1:
The patent segments the erasing operation into multiple phases with different voltage levels. First word lines receive a first voltage level during a first time period, then receive a second voltage level during a second time period, while other word lines receive a third voltage level during the second time period. This segmentation allows controlled threshold voltage reduction that maintains data retention while achieving erasure.
Solution Approach 2:
The patent employs periodic action by applying voltages in distinct time periods. The first voltage is applied during a first time period, followed by a second time period where different voltage levels are applied to different word lines. This temporal periodicity enables progressive erasure that balances speed and data retention.
2Reliability
If multiple voltage levels are applied to different word lines at the same time, then data erasure completeness is improved, but device complexity increases
Solution Approach 1:
The patent divides the word lines into different groups that receive different voltage levels during the second time period. First word lines receive a second voltage level while other word lines receive a third voltage level. This segmentation enables comprehensive erasure coverage while managing control complexity through organized voltage distribution.
Solution Approach 2:
The patent implements dynamic voltage control where the voltage levels applied to word lines change over time. During the first time period, all word lines receive the first voltage level. During the second time period, different word lines receive different voltage levels (second or third). This dynamic approach achieves complete erasure while adapting control complexity to the erasure progress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances data retention characteristics and facilitates faster data erasure by effectively reducing the threshold voltage of memory cell transistors through a phased voltage application strategy.
Implementation Method 1
a first voltage level is applied to a first plurality of word lines during a first time period, and a second voltage level is applied to a second plurality of word lines during a second time period
Data Source
AI summary
A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line. During a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line.