Memory Word Line Decoding with Local Repeaters for Timing
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines affects the operating voltages and overall performance of digital devices, particularly in memory macros, leading to timing issues.
Innovation Solution
A memory circuit design that includes a global control circuit generating pre-decoder signals and local control circuits with repeater circuits to increase the driving strength of local pre-decoder signals, improving timing by creating a local version of global pre-decoder signals and enhancing signal strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If ICs are made smaller and more complex, then integration density increases, but conductive line resistance increases affecting operating voltages and timing
Solution Approach 1:
The pre-decoder circuit is divided into global pre-decoder circuits and local pre-decoder circuits. The global pre-decoder receives address signals and generates global pre-decoder signals, which are then distributed to multiple local pre-decoder circuits. Each local pre-decoder generates local pre-decoder signals for its specific memory bank, reducing the distance and resistance impact on signal transmission.
Solution Approach 2:
Global pre-decoder signals act as intermediaries between the address signals and the local pre-decoder circuits. This intermediary layer allows the system to maintain timing performance by breaking down the direct long-distance signal path into shorter segments, mitigating the effect of conductive line resistance in highly integrated designs.
2Reliability
If conductive line resistance increases, then voltage drops increase, but adding more repeater circuits increases device complexity
Solution Approach 1:
Repeater circuits are strategically placed only where needed in the signal path, specifically between global pre-decoder circuits and local pre-decoder circuits, rather than uniformly throughout the entire circuit. This localized approach maintains signal integrity in high-resistance regions while minimizing overall circuit complexity.
Data Source
AI summary
A memory circuit includes a first local control circuit and a first set of word line post-decoder circuits. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to a first set of local address signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals in response to the first set of clock signals, and the first and second set of local pre-decoder signals.