Variable Word Line Pulse Widths for Low-Power Memory Reads
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Solution Overview
Problem
Conventional memory devices consume excessive power due to uniformly long word line pulse widths, which are necessary to ensure accurate read operations across memory cells with varying bit line lengths, leading to inefficient power usage.
Innovation Solution
The memory device generates word line signals with varying pulse widths based on the address of each memory cell, tailoring the pulse width to match the specific RC characteristics of each bit line, reducing power consumption without compromising read operation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniformly long word line pulse widths are used to ensure accurate read operations across all memory cells, then read operation accuracy is maintained, but power consumption increases excessively
Solution Approach 1:
The patent applies local quality by assigning different pulse widths to word line signals based on the specific bit line length and RC characteristics of each memory cell group. Memory cells are divided into multiple groups, with each group receiving a customized pulse width that matches its local electrical characteristics, thereby avoiding the waste of using uniformly long pulse widths for all cells.
Solution Approach 2:
The patent implements dynamics by making the word line signal pulse width variable rather than fixed. The pulse width is dynamically adjusted according to the addressed memory cell's bit line length, allowing the system to adapt the signal duration to the specific electrical characteristics of each memory cell group, thus optimizing both accuracy and power consumption.
2Reliability
If uniformly long word line pulse widths are used for all memory cells, then read accuracy is ensured, but power expenditure becomes inefficient
Solution Approach 1:
The patent divides memory cells into multiple groups with different bit line lengths, and assigns optimized pulse widths to each group based on its specific RC characteristics. This local quality approach ensures that each group receives the minimum necessary pulse width for accurate reading, eliminating unnecessary power expenditure from overly long pulse widths applied to cells with shorter bit lines.
Solution Approach 2:
The patent changes the pulse width parameter of the word line signal based on the memory cell group being accessed. By adjusting this critical parameter according to the bit line length and RC characteristics of each group, the system achieves accurate readings while minimizing energy loss from excessive pulse durations.
3Use of energy by moving object
If varying pulse widths are generated for different memory cells, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory cell array into multiple groups based on bit line length and RC characteristics. This segmentation allows the system to apply different pulse widths to different groups, reducing overall power consumption. The segmentation approach manages complexity by organizing cells into manageable groups with similar electrical characteristics.
Solution Approach 2:
The patent performs preliminary classification of memory cells into groups with similar RC characteristics before operation. This preliminary action enables the system to pre-determine the appropriate pulse width for each group, simplifying the signal generation process during actual read operations while still achieving power reduction through varying pulse widths.
Data Source
AI summary
A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.