3D Memory Word Line Thickness Layout to Prevent Short Circuits
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Solution Overview
Problem
The formation of contact holes in semiconductor memory devices can lead to short circuits between stacked word lines, which is a common issue during inspection and use.
Innovation Solution
The film thicknesses of some layers of the stacked word lines are thickened to reduce the occurrence of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact holes are formed in stacked word lines, then electrical connection is achieved, but short circuits between word lines occur
Solution Approach 1:
The patent applies local quality by making the film thickness of word lines non-uniform: word lines at positions where contact holes are formed have a greater film thickness than those at other positions. This localized thickening provides better insulation exactly where short circuits are most likely to occur, while maintaining thinner film thickness elsewhere to preserve device performance.
Solution Approach 2:
The patent changes the physical parameter of film thickness for word lines. By increasing the film thickness of specific word lines that are subjected to contact holes, the insulation capability is enhanced locally, preventing short circuits without requiring a uniform increase in all word line thicknesses.
2Reliability
If film thickness of word lines is increased, then short circuit resistance is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of uniformly increasing the film thickness of all word lines, the patent applies local quality by selectively thickening only those word lines that are positioned where contact holes are formed. This approach improves short circuit resistance where needed while avoiding the manufacturing complexity and performance degradation that would result from a uniform thickness increase across all word lines.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes the following structure. First word lines are stacked above a substrate. Second word lines are stacked above the first word lines. A selection gate line is provided above the second word lines. A first pillar penetrates the first word lines in a first direction orthogonal to an upper surface of the substrate. A second pillar penetrates the second word lines and the selection gate line in the first direction. The second word lines include an upper word line disposed around an upper layer portion of the second pillar, a middle word line disposed around a middle layer portion below the upper layer portion, and a lower word line disposed around a lower layer portion below the middle layer portion. A film thickness of the upper word line is thicker than that of the middle word line.


