3D Memory Word Line Staircase Layout for Higher Integration
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in increasing integration density due to the high cost of advanced pattern forming technologies, necessitating the development of three-dimensional semiconductor memory devices with improved reliability and integration density.
Innovation Solution
A semiconductor memory device with a staircase structure of word lines and interlayer insulating patterns, where word lines extend between regions and are connected by sub-gate electrodes and pads, allowing for increased integration density and reliability through a specific fabrication method involving mold structures and trimming processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density cannot be increased sufficiently due to area limitations and high cost of fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional semiconductor memory devices by stacking memory cells vertically. The stack structure includes multiple layers of word lines, bit lines, and insulating patterns arranged in the third dimension (vertical direction), enabling increased integration density without requiring finer lateral patterning.
2Quantity of substance
If three-dimensional semiconductor memory devices are implemented, then integration density is increased, but device complexity and fabrication difficulty increase
Solution Approach 1:
The three-dimensional stack structure is divided into multiple repeating units, each consisting of word lines, bit lines, and insulating patterns. This segmentation allows the complex three-dimensional structure to be constructed from standardized modular units, simplifying the fabrication process and reducing overall device complexity.
Solution Approach 2:
Mold structures are formed in advance during the fabrication process to define the three-dimensional stack geometry. These pre-formed molds guide subsequent deposition and etching steps, making the complex three-dimensional structure easier to fabricate by establishing the spatial framework beforehand.
3Quantity of substance
If fine pattern forming technology is advanced to increase integration, then integration density improves, but manufacturing cost increases significantly
Solution Approach 1:
The patent achieves increased integration density by utilizing the vertical dimension rather than pushing lateral pattern resolution to its limits. The stack structure with multiple layers in the third direction provides integration scaling without requiring extremely fine lateral patterning, thereby avoiding the exponential cost increase associated with advanced optical lithography.
Data Source
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AI summary
A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.