3D Memory Word-Line Layout with Step-Shaped Connection Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Manufacturing horizontally disposed capacitors in memory devices, such as DRAMs, poses challenges in aligning word lines (WLs) due to increased difficulty in matching them, hindering the manufacturing process and overall storage capacity.
Innovation Solution
A method involving the formation of active pillars and connection layers with step-shaped ends, where gate material layers connect on the same horizontal levels and are isolated on different levels, facilitating easy manufacturing and alignment of WLs, which are then used as WLs to enable electrical connection with peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are horizontally placed to increase storage density, then storage capacity is improved, but manufacturing precision of word lines deteriorates
Solution Approach 1:
The device is divided into a first area containing active pillars and a second area containing connection layers. This spatial segmentation allows independent optimization of transistor and capacitor regions, enabling horizontal capacitor placement while maintaining word line manufacturing precision through separate process control for each area.
Solution Approach 2:
The patent transitions from traditional planar capacitor placement to vertical stacking in the first direction, with capacitors extending in the second direction. This dimensional change allows capacitors to be horizontally disposed while active pillars maintain precise vertical alignment, resolving the conflict between storage density and manufacturing precision.
2Area of stationary object
If capacitors are horizontally disposed to increase storage density, then area utilization is improved, but device complexity increases
Solution Approach 1:
By dividing the device into distinct first and second areas with different structural configurations, the patent simplifies the manufacturing process for each region. The first area uses vertical active pillars while the second area uses horizontally disposed connection layers, allowing standardized processing steps for each segment rather than complex integrated patterning.
Solution Approach 2:
Different structural qualities are applied to different areas: the first area features vertically oriented active pillars optimized for transistor formation, while the second area features horizontally disposed connection layers optimized for capacitor integration. This local optimization reduces overall device complexity by allowing area-specific manufacturing approaches.
Data Source
AI summary
A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.