3D Memory Word-Line Stack with Stepped Support Structure
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Solution Overview
Problem
The stability of manufacturing processes and structural stability is compromised as the number of stacked word lines increases in three-dimensional semiconductor memory devices, affecting the integration and performance of the devices.
Innovation Solution
A semiconductor memory device is designed with a first stack and a second stack of conductive patterns separated by insulating layers, featuring a stepped structure and support pillars to enhance structural stability, along with a channel structure and memory layer to improve manufacturing process stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to increase the degree of integration, then the integration density is improved, but the manufacturing process stability and structural stability are deteriorated
Solution Approach 1:
The gate electrode stack is divided into multiple segments with different widths at different heights, forming a stepped structure. This segmentation reduces the overall width of the gate electrode stack while maintaining the number of stacked word lines, thereby improving manufacturing process stability and structural integrity without sacrificing integration density.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stepped structure by varying the width of gate electrode segments at different heights. This dimensional change allows for increased integration density through vertical stacking while controlling the horizontal footprint to maintain manufacturing stability.
2Quantity of substance
If the number of stacked word lines is increased to increase the degree of integration, then the integration density is improved, but the structural stability is deteriorated
Solution Approach 1:
The gate electrode stack is divided into multiple segments with different widths at different heights, forming a stepped structure. This segmentation reduces the overall width of the gate electrode stack while maintaining the number of stacked word lines, thereby improving manufacturing process stability and structural integrity without sacrificing integration density.
Solution Approach 2:
The patent employs asymmetric gate electrode segments where each segment has a different width, creating a stepped profile. This asymmetric design optimizes the structural distribution of stress and enhances structural stability while maintaining high integration density through efficient space utilization.
3Manufacturing precision
If the gate electrode stack width is reduced to improve manufacturing stability, then the manufacturing precision is improved, but the integration density is reduced
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stepped structure by varying the width of gate electrode segments at different heights. This dimensional change allows for increased integration density through vertical stacking while controlling the horizontal footprint to maintain manufacturing stability.
Solution Approach 2:
The gate electrode stack is divided into multiple segments with different widths at different heights, forming a stepped structure. This segmentation reduces the overall width of the gate electrode stack while maintaining the number of stacked word lines, thereby improving manufacturing process stability and structural integrity without sacrificing integration density.
Data Source
AI summary
A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.


