Memory Array Word-Line Voltage Control for In-Memory Accuracy
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Solution Overview
Problem
The classical Von Neumann computing architecture is bottlenecked by high power consumption and limited processing speed due to frequent data migration and memory bandwidth limitations, exacerbated by big data and artificial intelligence applications.
Innovation Solution
A semiconductor device with a memory array and peripheral circuit that applies carefully controlled program and pass voltages to adjacent word lines during programming to stabilize threshold voltages of memory cells, reducing electron diffusion and improving accuracy in in-memory computing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high program voltages are applied to adjacent word lines during programming, then programming speed is improved, but electron diffusion between adjacent memory cells increases, reducing threshold voltage stability and computing accuracy
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their position relative to the selected word line. Specifically, it uses a first program voltage for the selected word line, a second program voltage (lower than the first) for first adjacent word lines, and a third program voltage (lower than the second) for second adjacent word lines. This localized voltage differentiation reduces electron diffusion from adjacent word lines while maintaining effective programming of the selected word line, thereby resolving the contradiction between programming speed and threshold voltage stability.
Solution Approach 2:
The patent dynamically adjusts the program voltage parameter based on the distance from the selected word line. By changing the voltage magnitude according to spatial position (selected word line receives highest voltage, first adjacent receives moderate voltage, second adjacent receives lowest voltage), the system optimizes both programming efficiency and threshold voltage stability, preventing electron diffusion while ensuring adequate programming speed.
2Adaptability or versatility
If data is frequently migrated between memory and processor in Von Neumann architecture, then processing flexibility is maintained, but power consumption increases and processing speed decreases
Solution Approach 1:
The patent merges the memory array with in-memory computing capabilities by integrating computing units directly within the memory structure. This allows computational operations to be performed within the memory array itself, eliminating the need for frequent data migration between separate memory and processor components. The merging of storage and computing functions maintains processing flexibility while significantly reducing power consumption associated with data transfer.
Solution Approach 2:
The patent transitions from the traditional Von Neumann architecture (separate memory and processor dimensions) to a computing-in-memory architecture where computing capabilities are embedded within the memory dimension. This dimensional integration enables data to be processed in-place without physical migration, reducing power consumption while preserving the adaptability needed for various computing tasks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability and accuracy of in-memory computing by minimizing voltage differences between adjacent word lines, thereby improving data retention and computing performance.
Implementation Method 1
during a program phase of a first program loop, apply a first program voltage to a first word line and apply a second program voltage to a second word line adjacent to the first word line
Implementation Method 2
reducing electron diffusion and improving accuracy in in-memory computing
Data Source
AI summary
According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit may be configured to, during a program phase of a first program loop, apply a first program voltage to a first word line and apply a second program voltage to a second word line adjacent to the first word line. An absolute value of a difference between the first program voltage and the second program voltage may be less than a first preset value. The peripheral circuit may be configured to, during the program phase of the first program loop, apply a first pass voltage to a third word line. The first pass voltage may be less than the first program voltage, and the first pass voltage may be less than the second program voltage.