Memory Word-Line Circuit With Temperature-Coefficient Voltage Switching
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Solution Overview
Problem
Existing memory devices face high power consumption and reliability issues due to constant high voltage levels required for word lines, particularly impacting metal-oxide-semiconductor field-effect transistors (MOSFETs) with time-dependent dielectric breakdown properties.
Innovation Solution
A temperature coefficient modulation (TCM) circuit that generates output voltages with positive or negative temperature coefficients depending on the operation mode of the memory array, optimizing power management by adjusting the word line voltage accordingly during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word lines are maintained at high voltage levels for memory operations, then memory access reliability is improved, but power consumption increases and MOSFET reliability deteriorates due to TDDB effects
Solution Approach 1:
The patent implements dynamic voltage adjustment by switching between a first voltage level during read operations and a second voltage level during write operations. The voltage level is dynamically changed based on the operation type, avoiding continuous high voltage application and thereby reducing power consumption and TDDB effects while maintaining reliable memory access.
Solution Approach 2:
The patent changes the voltage parameter based on operation mode. During read operations, a first voltage level is applied to ensure reliable data reading, while during write operations, a second voltage level is applied to ensure reliable data writing. This parameter change optimizes both power consumption and reliability for different operation types.
2Reliability
If word lines are maintained at high voltage levels, then memory operation reliability is improved, but MOSFET integrity deteriorates due to time-dependent dielectric breakdown
Solution Approach 1:
The patent dynamically adjusts the voltage level applied to word lines based on the operation type. By switching between a first voltage level for reads and a second voltage level for writes, the patent minimizes the duration and magnitude of high voltage stress on MOSFETs, thereby reducing TDDB effects while maintaining operation reliability.
Solution Approach 2:
The patent employs periodic switching between different voltage levels according to read and write operation cycles. This periodic action ensures that high voltage is applied only when necessary for write operations, while read operations use lower voltage, thereby periodically reducing the cumulative TDDB stress on MOSFETs.
3Reliability
If high voltage levels are applied to word lines, then write operation reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage switching where a second voltage level is applied during write operations to ensure reliable data writing, and a first voltage level is applied during read operations to reduce power consumption. This dynamic adjustment ensures high voltage is used only when necessary for writes, optimizing the trade-off between write reliability and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption on word lines, enhances the efficiency of memory operations, and minimizes voltage stress on MOSFETs, thereby improving the reliability of memory devices across a wide temperature range.
Implementation Method 1
A temperature coefficient modulation (TCM) circuit that switches between positive and negative temperature coefficients for output voltages during read and write operations, respectively
Data Source
AI summary
A method includes: providing a modulation circuit and a driving circuit, the modulation circuit configured to generate a temperature-dependent voltage and provide the same to the driving circuit; determined an operation mode of a memory array; providing a first current corresponding to a positive temperature coefficient by the driving circuit in response to the operation mode being a read operation on the memory array; and providing a second current corresponding to a negative temperature coefficient by the driving circuit in response to the operation mode being a write operation on the memory array.