Memory Bank Write Abort for Lower Read Latency
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Solution Overview
Problem
Existing high-density memory arrays, such as 3-D NOR memory arrays, face challenges in reducing read latency due to the nature of quasi-volatile memory cells requiring less frequent refreshes, which can lead to inefficiencies in data access and increased power consumption.
Innovation Solution
Implementing a memory system with a controller device that can issue write abort operations to terminate ongoing write operations in specific memory banks, allowing for immediate read operations from the same bank, thereby optimizing data access and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write operations are allowed to complete normally in high-density memory arrays, then data integrity is maintained, but read latency increases significantly for subsequent read requests to the same memory bank
Solution Approach 1:
The patent implements dynamic write abort capability that allows the memory controller to terminate ongoing write operations based on real-time read requests. The system dynamically switches between completing writes (for integrity) and aborting writes (for latency reduction) depending on the operational context and priority of read operations.
Solution Approach 2:
The patent introduces preliminary abort decision logic in the memory controller that can preemptively terminate write operations before they complete, when a read request to the same memory bank is detected. This preliminary action prevents the read latency penalty by stopping the write operation before it blocks the read path.
2Loss of time
If write operations are terminated early to reduce read latency, then read operations can proceed immediately, but the write operation must be resumed or retried, increasing overall write complexity
Solution Approach 1:
The patent implements feedback mechanisms where the memory controller tracks aborted write operations and their status. When a write is aborted, the controller maintains information about the pending write and can resume or retry it after the read operation completes, using feedback from the read completion event to restore write operations.
Solution Approach 2:
The patent extracts the write abort and resume functionality as a separate control mechanism independent of the normal write completion path. This allows write operations to be interrupted and restored without fundamentally changing the core write logic, isolating the complexity to a specific abort/resume handling module.
3Productivity
If write abort functionality is implemented in the memory controller, then read operations can proceed without waiting for write completion, but the controller logic becomes more complex
Solution Approach 1:
The patent segments the memory controller logic into distinct modules: one handling normal write operations, another detecting read conflicts, and a third managing write abort/resume decisions. This segmentation allows write abort functionality to be added without monolithically increasing controller complexity, as each segment handles a specific aspect independently.
Solution Approach 2:
The patent designs the write abort mechanism to serve multiple functions: reducing read latency, maintaining write data integrity through retry logic, and providing fine-grained control over memory bank access. This multi-functionality justifies the added controller complexity by delivering multiple performance benefits from a single architectural feature.
Data Source
AI summary
A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller device is configured to issue to the memory device a write command and a write termination command, where the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the write operation. In one embodiment, the controller device issues a write abort command as the write termination command to terminate a write operation in progress at a certain memory bank of the memory device in order to issue a read command to read data from the same memory bank. The terminated write operation can resume after the completion of the read operation.