Memory Write Error Detection Using Address-Dependent ECC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for reading and writing data in memory systems are prone to errors, particularly accidental or deliberate errors during data writing, which can compromise the operation of electronic systems, and there is a need for more reliable and efficient error detection and correction mechanisms.
Innovation Solution
A method involving the splitting of a binary word into two parts, with one part written in a first memory circuit and the other in a second circuit, using an error correcting or detecting code dependent on the datum and address, allowing for error detection and correction by comparing internal control signals and recombining the parts to verify data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written in a single memory circuit, then the writing operation is simple and fast, but error detection and correction capabilities are limited
Solution Approach 1:
The binary word is segmented into at least two parts, with each part being written to a different memory circuit. This segmentation allows the system to distribute data storage across multiple circuits, enabling error detection and correction by comparing results from different circuits while maintaining relatively simple individual circuit designs.
Solution Approach 2:
The invention creates redundant copies of data parts across multiple memory circuits. By writing different parts of the binary word to different circuits and using error correcting or detecting codes, the system can detect and correct errors by comparing the copied data, thereby improving reliability without requiring completely new memory architecture.
2Reliability
If error correcting or detecting code is added to the binary word, then error detection capability is improved, but the data storage space is reduced
Solution Approach 1:
By segmenting the binary word into multiple parts and distributing them across different memory circuits, the error correcting or detecting code overhead is distributed rather than concentrated. This allows the system to maintain better effective storage capacity while still providing comprehensive error detection capability across the entire data word.
Solution Approach 2:
The error correcting or detecting code is applied locally to different parts of the binary word that are stored in different memory circuits. This local application of error correction allows each memory circuit to operate efficiently with smaller code overhead, while the combination provides global error detection capability for the complete binary word.
3Reliability
If multiple memory circuits are used to store different parts of binary word, then error detection is improved, but the writing operation becomes more complex
Solution Approach 1:
The binary word is divided into segments that can be independently written to different memory circuits using standard writing operations. This segmentation approach maintains simplicity in individual writing operations while achieving improved error detection through the distributed architecture.
Solution Approach 2:
The invention combines multiple simple writing operations to different memory circuits into a unified error detection system. By merging the results from different circuits and applying error correcting or detecting codes, the system achieves high error detection accuracy while keeping individual writing operations relatively simple.
4Reliability
If internal control signals are compared between memory circuits, then error detection capability is enhanced, but the system complexity increases
Solution Approach 1:
The invention copies control signals across multiple memory circuits and compares them to detect errors. This copying approach allows error detection through simple signal comparison rather than complex analysis mechanisms, maintaining relatively low system complexity while enhancing error detection capability.
Solution Approach 2:
The comparison of internal control signals between memory circuits creates a feedback mechanism that detects errors in real-time during writing operations. This feedback-based error detection uses relatively simple signal comparison logic rather than complex error analysis, thereby enhancing reliability without significantly increasing system complexity.
Data Source
AI summary
A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.