Memory Write Assist Circuit for Reduced Power Supply Voltage
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Solution Overview
Problem
Existing memory technologies, such as SRAMs, face challenges in reducing bitcell power supply voltage during write operations, as lowering the voltage initially appears to conserve power but results in increased power consumption due to the subsequent recharging of the array to the original voltage level.
Innovation Solution
Implementing a memory system where the bitcell power supply voltage can be selectively reduced on a memory block or column basis during write operations, with the reduced voltage chosen based on the specific needs of the memory cells, using a write assist circuit with trimmable resistors and transistors to manage the voltage, ensuring efficient power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bitcell power supply voltage is reduced during a write operation, then write capability is improved, but power consumption increases due to subsequent voltage restoration
Solution Approach 1:
The patent applies different power supply voltages to different portions of the memory array based on their specific write requirements. Memory blocks or columns that require reduced voltage for successful writes receive only the necessary voltage reduction, while other portions maintain normal voltage levels, avoiding unnecessary power consumption from blanket voltage restoration across the entire array.
Solution Approach 2:
The memory array is divided into separate memory blocks or columns, each with independent voltage control through selection circuits. This segmentation allows selective application of reduced voltage to only those specific segments that require it for write operations, rather than applying voltage changes to the entire array, thereby minimizing power consumption during voltage restoration.
2Reliability
If the bitcell power supply voltage is reduced during a write operation, then difficult-to-write logic states can be achieved, but the array requires significant power for voltage restoration
Solution Approach 1:
The invention provides tailored voltage conditions to specific memory blocks or columns that contain cells with imbalanced transistors. By using selection circuits to identify and apply reduced voltage only to affected segments, the system achieves reliable writes for difficult logic states without requiring full-array voltage restoration, thereby reducing restoration power requirements.
Solution Approach 2:
The power supply voltage is dynamically adjusted based on the specific write requirements of different memory segments. Selection circuits enable real-time control, allowing the system to apply reduced voltage during write operations to blocks with imbalanced transistors, then maintain or selectively restore voltage only where necessary, optimizing the balance between write capability and power consumption.
Data Source
AI summary
A memory includes a selection circuit and a write assist circuit. The selection circuit has a first input, a second input coupled to a first power supply voltage terminal, an output coupled to a power supply terminal of each of a plurality of memory cells, and a control input for receiving a write assist control signal. The write assist circuit is coupled to the first input of the selection circuit for reducing a voltage at the power supply terminal of each of the plurality of memory cells during a write operation and in response to an asserted write assist enable signal. The write assist circuit comprises a P-channel transistor and a bias voltage generator. The P-channel transistor is for reducing the voltage at the power supply terminal of each of the plurality of memory cells during the write operation. The bias voltage generator is for providing a variable bias voltage to the P-channel transistor.