Memory Write Assist Power Supply Collapse Feedback Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In scaled technologies, maintaining memory cell stability and write margin while reducing power supply collapse-induced cross-over current is challenging, especially in low power designs where extended voltage collapse increases write power consumption.
Innovation Solution
The implementation of power supply collapse circuits with a feedback mechanism and self-timed voltage collapse, utilizing hysteresis-based and capacitor-based architectures to reduce cross-over current consumption and provide tunable power supply collapse voltage levels, ensuring minimal power consumption during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply voltage is collapsed during write operation to enhance write margin, then write margin is improved, but cross-over current increases significantly
Solution Approach 1:
The patent implements a feedback mechanism using a Schmitt trigger that monitors the power supply voltage and controls the collapse timing. The feedback loop detects when the power supply voltage reaches a predetermined threshold and automatically terminates the collapse operation, preventing excessive cross-over current while maintaining sufficient voltage reduction to enhance write margin.
Solution Approach 2:
The patent dynamically changes the power supply voltage parameter during write operations by collapsing it to a predetermined threshold level and then restoring it. This parameter change is controlled through feedback mechanisms that adjust the voltage based on operational needs, enhancing write margin while minimizing energy loss through precise control of the collapse duration and depth.
2Stability of the object's composition
If power supply collapse duration is extended to maintain stability in partially selected cells, then memory cell stability is improved, but write power consumption increases
Solution Approach 1:
The feedback mechanism continuously monitors the state of memory cells during power supply collapse and automatically terminates the collapse when predetermined conditions are met. This ensures that partially selected cells maintain their stability while preventing extended collapse that would increase write power consumption, achieving a balance between stability and energy efficiency.
Solution Approach 2:
The patent establishes predetermined voltage thresholds and collapse duration parameters before the write operation begins. These preliminary settings define the exact conditions under which the power supply collapse should terminate, ensuring that memory cell stability is maintained without requiring extended collapse periods that would increase power consumption.
3Reliability
If power supply collapse depth is increased to enhance write margin, then write margin is improved, but cross-over current increases
Solution Approach 1:
The patent optimizes the power supply voltage parameter by collapsing it to a specific predetermined threshold level rather than allowing unlimited voltage reduction. This controlled parameter change achieves sufficient voltage reduction to enhance write margin while preventing the excessive voltage collapse that would cause significant cross-over current increase.
Solution Approach 2:
The feedback mechanism monitors the power supply voltage during collapse and automatically terminates the operation when the predetermined threshold is reached. This feedback control ensures that the collapse depth is precisely limited, achieving write margin enhancement without allowing the voltage to drop to levels that would cause excessive cross-over current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces cross-over current consumption by up to 40% compared to traditional methods, allowing for efficient write operations with negligible power consumption during power supply collapse, thereby enhancing memory cell stability and write margin without increasing overall power usage.
Implementation Method 1
a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node
Implementation Method 2
utilizing hysteresis-based and capacitor-based architectures
Implementation Method 3
utilizing hysteresis-based and capacitor-based architectures
Data Source
AI summary
Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.