Memory Device Write Auxiliary Circuit for Power and Speed
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Solution Overview
Problem
Existing memory devices face challenges in increasing the speed of write operations while reducing power consumption, particularly due to increased integration density and demand for improved static noise margin, write margin, and sense margin.
Innovation Solution
The memory device incorporates a write auxiliary circuit connected to a first auxiliary line for supplying cell power voltage and a second auxiliary line for switching the supply direction of the cell power voltage, allowing for sequential supply of the voltage from the first bit cell to the second bit cell, thereby enhancing write operation speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the cell power voltage is supplied uniformly to all bit cells simultaneously, then the write operation can be performed across the entire bit cell array, but the write operation speed is limited and power consumption is high
Solution Approach 1:
The bit cell array is divided into multiple regions along the column direction, with different cell power voltage levels applied to different regions. The write auxiliary circuit selectively lowers the cell power voltage for bit cells spaced apart from the write driver (first bit cells) while maintaining normal voltage for bit cells adjacent to the write driver (second bit cells), enabling segmented voltage control that improves write speed and reduces power consumption.
Solution Approach 2:
Different cell power voltage levels are applied to different spatial regions of the bit cell array based on their distance from the write driver. First bit cells receive a lowered cell power voltage while second bit cells receive normal cell power voltage, creating local quality variations that optimize write operations for each region's specific electrical characteristics.
2Use of energy by moving object
If the cell power voltage level is lowered for all bit cells, then power consumption is reduced, but the stability of the stored data and operation reliability decrease
Solution Approach 1:
The cell power voltage is selectively lowered only for first bit cells that are spaced apart from the write driver, while second bit cells adjacent to the write driver maintain normal cell power voltage. This local differentiation reduces power consumption in regions where it is most needed while preserving data stability and operation reliability in regions where normal voltage ensures proper functioning.
Solution Approach 2:
Instead of lowering the cell power voltage for all bit cells, the write auxiliary circuit applies voltage reduction only to the extent necessary for first bit cells, leaving second bit cells at normal voltage levels. This partial action achieves power savings without excessively compromising the overall reliability of the memory device.
3Stability of the object's composition
If more auxiliary lines are added to supply cell power voltage to all bit cells, then uniform voltage supply is achieved, but device complexity increases
Solution Approach 1:
The auxiliary line system is segmented into multiple paths: a first auxiliary line that supplies cell power voltage to second bit cells adjacent to the write driver, and a second auxiliary line that supplies lowered cell power voltage to first bit cells spaced apart from the write driver. This segmentation enables differentiated voltage supply without requiring a completely complex new architecture.
Solution Approach 2:
The write auxiliary circuit acts as an intermediary between the power supply and the bit cells, selectively adjusting the cell power voltage level for different regions. This intermediary component manages the complexity by centralizing the voltage control logic rather than distributing it across multiple independent auxiliary lines for each bit cell.
Data Source
AI summary
A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.