Semiconductor Memory Write-Back Transistor Backgate Bias
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Solution Overview
Problem
Semiconductor memory devices using destructive read systems face increased time requirements for write-back operations due to the need to handle multi-bit data, where the transfer of write-back potentials to memory cells is delayed by the time it takes to fix sense node potentials to high or low levels, and the insufficient voltage applied between the gate and source of write-back transistors affects the transfer of write-back potentials.
Innovation Solution
The use of backgate bias effects to control the threshold voltages of write-back transistors, allowing for high-speed transfer of write-back potentials by changing backgate potentials to facilitate the turn-on of transistors before sense amplifiers operate, and the implementation of N-channel transistors in write-back potential transfer circuits to reduce the area of the read circuit and decrease parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is stored in memory cells, then storage capacity is improved, but write-back operation time increases
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block containing independent memory cells that can be read and written back simultaneously. This segmentation allows parallel processing of multi-bit data, reducing the overall write-back operation time while maintaining high storage capacity.
Solution Approach 2:
Sense node potentials are fixed to high or low levels before the write-back operation begins. This preliminary action prepares the read circuit in advance, allowing the write-back of multi-bit data to proceed without delay and significantly reducing write-back operation time.
2Measurement precision
If sense node potentials are fixed after reading, then reading accuracy is maintained, but write-back transfer speed decreases
Solution Approach 1:
The sense node potentials are fixed to high or low levels immediately after the read operation completes, before the write-back operation begins. This preliminary fixation ensures accurate reading while preparing the circuit for fast write-back transfer, resolving the contradiction between reading accuracy and write-back speed.
Solution Approach 2:
The fixing of sense node potentials and the write-back operation are performed in continuous sequence without idle time. This continuous operation maintains reading accuracy while maximizing write-back transfer speed by eliminating waiting periods between operations.
3Speed
If sufficient voltage is applied between gate and source of write-back transistors, then transfer speed is improved, but power consumption increases
Solution Approach 1:
Different voltage levels are applied to different write-back transistors based on their specific requirements for transferring write-back potentials. This localized voltage optimization ensures sufficient transfer speed for each transistor while minimizing overall power consumption by avoiding excessive voltage application throughout the entire circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required for write-back operations by ensuring sufficient voltage is applied between the gate and source of write-back transistors, improving reading performance and enabling faster transfer of write-back potentials, thus addressing the delays associated with multi-bit data handling.
Implementation Method 1
The use of backgate bias effects to control the threshold voltages of write-back transistors, allowing for high-speed transfer of write-back potentials by changing backgate potentials to facilitate the turn-on of transistors
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.