Memory Write Acceleration by Pausing Background Operations
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Solution Overview
Problem
Non-volatile memory devices face challenges in ensuring data integrity during power loss events, particularly in vehicle DVR systems, where critical video data may not be successfully written to memory due to insufficient power loss protection, leading to permanent data loss.
Innovation Solution
Implementing a system that pauses background operations in the memory device upon detecting a potential event, allowing for increased write speeds to ensure critical data is written before power loss, using internal firmware manipulation to enhance write speed without relying on large capacitors or high-cost management chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device operates at normal write speeds with background operations running, then power consumption is reduced and device complexity is maintained, but data integrity during power loss events deteriorates due to insufficient time to complete critical write operations
Solution Approach 1:
The system performs preliminary detection of power loss events and proactively pauses background operations before the actual power loss occurs. This preliminary action creates a protective window that ensures critical write operations can complete successfully, improving data integrity without requiring complex hardware modifications.
Solution Approach 2:
The memory device dynamically adjusts its operating mode based on detected events. When a power loss event is detected, the system transitions from normal operation with background tasks running to an enhanced protection mode where background operations are paused and write speeds are increased. This dynamic adaptation resolves the contradiction by only activating the more complex protective measures when actually needed.
2Reliability
If large capacitors or high-cost management chips are used to protect against power loss, then data integrity improves, but device complexity and cost increase
Solution Approach 1:
The memory device uses its own internal firmware to detect power loss events and automatically pause background operations. This self-service approach eliminates the need for external protection circuits, large capacitors, or expensive management chips, achieving reliable power loss protection while maintaining simple device architecture.
Solution Approach 2:
The patent replaces physical hardware protection mechanisms (such as capacitors and dedicated protection circuits) with a firmware-based software solution. The firmware monitors power conditions and controls operation pausing through logical operations, substituting mechanical/electrical protection systems with a more flexible and cost-effective software-based approach.
3Speed
If background operations are paused during potential events, then write speed increases to ensure data completion, but productivity decreases due to operation interruptions
Solution Approach 1:
The system applies preliminary anti-action by pausing background operations in anticipation of power loss events. This prevents the harmful effect of incomplete writes during power loss while minimizing productivity impact by only interrupting operations when events are detected, rather than continuously pausing operations.
Solution Approach 2:
The system applies partial action by selectively pausing only the background operations that would interfere with critical write completion, rather than halting all operations. This partial interruption approach achieves sufficient write speed enhancement for data protection while maintaining overall system productivity through selective rather than universal operation pausing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures higher data integrity by successfully writing crucial video data to memory before power outage, reducing memory design complexity and costs, and enhancing customer experience by preserving vital evidence.
Implementation Method 1
applying a high positive voltage, which may be referred to as a 'program voltage,' a 'programming power voltage,' or 'VPP,' to a control gate to generate Fowler-Nordheim tunneling (referred to as 'F-N tunneling') between a floating gate and the semiconductor substrate. When F-N tunneling is occurring, electrons of the bulk area are accumulated on the floating gate
Data Source
AI summary
In some implementations, a memory device may receive, from a host device, a signal indicative of a potential event. The memory device may pause, based on the signal, a background operation of the memory device. The memory device may perform a write operation to write data to the memory while the background operation is paused, wherein a write speed associated with the write operation is an increased write speed, as compared to a default write speed, based on the background operation being paused during the write operation.