Computational Memory Write Circuit for Bit-Line Data Shifting
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Solution Overview
Problem
Existing memory cells can only perform simple logical functions when connected to the same read bit line, limiting the complexity of logical operations that can be achieved across multiple memory cells.
Innovation Solution
Incorporating additional write processing circuitry into a processing array with computational memory cells, allowing data shifting between bit line sections and enabling more complex logical functions through read/write logic and data inversion control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cells are connected to the same read bit line to perform logical functions, then logical computation capability is improved, but the complexity of logical functions that can be performed is limited
Solution Approach 1:
The patent makes memory cells perform multiple functions by enabling them to execute different logical operations (AND, OR, XOR, XNOR, NAND, NOR) through configuration of read bit line connections and control signals, rather than requiring separate dedicated circuits for each logical function. This multi-functionality approach increases adaptability while managing device complexity.
Solution Approach 2:
The patent introduces dynamic reconfigurability where the logical function performed by memory cells can be changed on-the-fly through control signals and bit line connections, allowing the system to adapt between different computational tasks without physical reconfiguration. This dynamic approach enables versatile logical computation within a fixed hardware structure.
2Adaptability or versatility
If additional write processing circuitry is added to enable data shifting between bit line sections, then complex logical functions are enabled, but device complexity increases
Solution Approach 1:
The patent combines write processing circuitry with existing memory cell structures, integrating data shifting capabilities into the bit line architecture. By merging the write processing functions with the memory array structure, the patent enables complex data processing while minimizing the increase in overall device complexity through shared hardware resources.
Solution Approach 2:
The patent introduces intermediate control circuitry that mediates between simple memory cells and complex computational requirements. These intermediary components (write logic, control signals, bit line switching) enable complex logical functions without requiring fundamental changes to the basic memory cell structure, thus managing the trade-off between capability and complexity.
Data Source
AI summary
A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.