Memory Write Buffering for Unaligned Logical Address Updates
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Solution Overview
Problem
As memory devices increase in capacity, the use of larger logical unit sizes for L2P tables increases the likelihood of unaligned write requests, leading to additional processing operations and resource consumption for smaller data sizes.
Innovation Solution
The memory device is configured to use a larger logical unit size for L2P table entries while allowing other components to operate with a smaller unit size, utilizing a bundled unit for LBA translation and temporary memory allocation, simplifying operations for unaligned write requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger logical unit sizes are used for L2P table entries to increase memory capacity, then memory capacity is improved, but the likelihood of unaligned write requests increases leading to additional processing operations and resource consumption
Solution Approach 1:
The patent segments the logical unit into multiple smaller units within a bundled unit structure. When a write request targets a logical address, the system identifies which specific unit within the bundled unit needs modification, allowing precise operations on smaller data sizes while maintaining the larger logical unit structure for L2P table entries. This segmentation enables efficient handling of unaligned write requests by operating only on the necessary portion rather than the entire logical unit.
2Quantity of substance
If larger logical unit sizes are used for L2P table entries, then memory capacity is improved, but processing time for handling unaligned write requests increases
Solution Approach 1:
The patent performs preliminary actions by pre-organizing data into bundled units with identified unit positions and preparing the mapping structure in advance. When a write request arrives, the system can quickly determine which unit within the bundled unit needs modification without requiring extensive processing. The preliminary organization of data into manageable units with tracked positions enables rapid identification and operation on the specific target, reducing processing time for unaligned write requests.
3Quantity of substance
If larger logical unit sizes are used for L2P table entries, then memory capacity is improved, but resource consumption for handling smaller data sizes increases
Solution Approach 1:
The patent applies local quality by making different parts of the system operate at different granularities. The L2P table uses larger logical unit sizes for capacity efficiency, while the actual write operations work with smaller unit sizes within bundled units. This local differentiation allows the system to optimize each component for its specific function: the L2P table for compact storage and the bundled unit structure for efficient processing, thereby reducing overall resource consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing resources and time required for handling unaligned write requests by enabling efficient data handling with aligned operations for smaller data sizes.
Implementation Method 1
applying a high positive voltage, which may be referred to as a 'program voltage,' a 'programming power voltage,' or 'VPP,' to a control gate to generate Fowler-Nordheim tunneling (referred to as 'F-N tunneling') between a floating gate and the semiconductor substrate. When F-N tunneling is occurring, electrons of the bulk area are accumulated on the floating gate by an electric field of VPP applied to the control gate to increase a threshold voltage of the memory cell.
Implementation Method 2
An erasing operation of the memory cell is concurrently performed in units of sectors sharing the bulk area (referred to as 'blocks'), by applying a high negative voltage, which may be referred to as an 'erase voltage' or 'Vera,' to the control gate and a configured voltage to the bulk area to generate the F-N tunneling. In this case, electrons accumulated on the floating gate are discharged into the source area, so that the memory cells have an erasing threshold voltage distribution.
Data Source
AI summary
Implementations described herein relate to memory device operations for unaligned write operations. In some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. The memory device may allocate a set of buffers for the write command. The memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. The memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. The memory device may write the data unit to memory indicated by the set of physical addresses.