Non-Volatile Memory Write Circuit Background Verification
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in achieving high-performance write operations without incurring foreground verification latency, as they often require series of programming pulses and foreground verification to prevent under- and over-programming, which increases latency and wear on memory cells.
Innovation Solution
Implementing a system that applies a single initial programming pulse to a group of memory cells, followed by background verification to identify and correct under-programmed cells, thereby ensuring accurate programming without foreground verification latency, using a memory device with a write circuit and verification logic to apply corrective pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If series of programming pulses and foreground verification are used to prevent under- and over-programming, then programming accuracy is improved, but write latency increases
Solution Approach 1:
The patent applies preliminary action by performing verification in the background after the foreground write operation completes. The system executes a foreground write operation to store data, then subsequently performs background verification to detect and correct any under-programmed cells. This separates the time-critical write operation from the verification process, achieving both high speed and accuracy.
Solution Approach 2:
The patent segments the write operation into two independent phases: foreground write operation and background verification. The foreground phase handles rapid data programming without verification overhead, while the background phase performs thorough verification and correction. This segmentation allows each phase to be optimized independently for speed and accuracy.
2Reliability
If series of programming pulses are applied to ensure accurate programming, then programming reliability is improved, but wear on memory cells increases
Solution Approach 1:
The patent applies partial action by using a single programming pulse instead of multiple pulses. The background verification process identifies only the cells that were under-programmed, and corrective pulses are applied only to those specific cells. This partial correction approach reduces overall wear compared to applying multiple pulses to all cells.
Solution Approach 2:
The system performs self-service through background verification that automatically detects and corrects programming errors without external intervention. The verification logic identifies under-programmed cells and triggers corrective programming only where needed, allowing the memory system to self-correct errors and maintain reliability with minimal additional wear.
3Measurement precision
If foreground verification is performed to ensure data integrity, then data accuracy is improved, but write performance decreases
Solution Approach 1:
The patent performs verification as a preliminary background task after the foreground write operation completes. The system acknowledges the write command immediately after the programming pulse, then performs verification in the background. This ensures data accuracy through verification while maintaining high write performance by not blocking the foreground operation.
Solution Approach 2:
The patent maintains continuity of useful action by performing background verification continuously after foreground writes complete. The verification process operates independently and continuously checks programmed data, ensuring data accuracy without interrupting the continuous flow of foreground write operations. This keeps the system productive while maintaining accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-performance write operations with reduced latency and minimized wear on memory cells by ensuring accurate programming without the need for foreground verification, while preventing under- and over-programming through background validation.
Implementation Method 1
a write circuit to apply a single programming pulse to a group of memory cells
Implementation Method 2
verification logic to identify under-programmed memory cells and apply a corrective programming pulse
Data Source
AI summary
A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.