Semiconductor Memory Write Circuit Low Voltage Speed
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in performing high-speed write operations at lower voltages without increasing the word line activation period at normal voltage, leading to reduced operating frequency and the need for external commands based on operating voltage.
Innovation Solution
A semiconductor memory device with a write circuit comprising two N-type transistors connected directly to bit lines and a column selecting and data input circuit that generates logical products of data and write signals to control the transistors, allowing high-speed potential pulling on bit lines at lower voltages without extending the word line activation period, and optionally setting bit line potentials to negative for enhanced writing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the word line activation period is increased to enable sufficient potential pulling on bit lines at lower voltage, then writing speed at lower voltage is improved, but operating frequency at normal voltage is reduced
Solution Approach 1:
The patent applies dynamics by making the write circuit configuration adaptable to different operating voltages. At lower voltages, the circuit dynamically switches to a configuration that provides sufficient drive strength for bit line potential pulling, while at normal voltage it operates in a high-speed mode. This dynamic adaptation resolves the contradiction between writing speed at low voltage and operating frequency at normal voltage.
Solution Approach 2:
The patent changes circuit parameters (transistor sizing, circuit topology) based on operating voltage conditions. The write circuit includes transistors with specifically designed sizes and configurations that optimize performance for low-voltage operation without sacrificing normal-voltage speed. This parameter optimization allows the circuit to achieve sufficient potential pulling at low voltage while maintaining high operating frequency at normal voltage.
2Use of energy by moving object
If conventional write circuits are used at lower voltage, then power consumption is reduced, but writing speed deteriorates due to insufficient drive strength
Solution Approach 1:
The patent optimizes transistor sizes and circuit parameters specifically for low-voltage operation. The write circuit includes transistors with enlarged sizes and optimized configurations that provide sufficient drive strength at lower voltages to achieve adequate writing speed, while still maintaining lower power consumption compared to conventional high-voltage operation. This parameter optimization resolves the contradiction between power consumption and writing speed at lower voltage.
3Reliability
If the bit line potential is pulled down strongly to ensure data writing, then writing reliability is improved, but data integrity in unselected cells deteriorates due to noise coupling
Solution Approach 1:
The patent applies local quality by selectively activating write circuits only for the specific bit lines and word lines that need to be written. The column selecting circuit ensures that only the targeted memory cells are affected by the strong potential pulling, while other cells remain isolated. This localized approach allows strong potential pulling for reliable writing in selected cells without causing noise coupling to unselected cells, thus resolving the contradiction between writing reliability and data integrity.
Data Source
AI summary
A semiconductor memory device capable of performing a high-speed write operation at lower voltage without increasing the word line activation period at normal voltage. The memory device has a write circuit including two NMOS transistors respectively having sources connected to ground potential. One of the transistors has a drain connected to one of a pair of bit lines, and the other transistor has a drain connected to the other bit line. The memory device also has a column selecting and data input circuit which generates a logical product of inverted data of data to be written and a write column selecting signal, inputs the logical product to the gate of the one transistor, generates a logical product of the data to be written and the write column selecting signal, and inputs the logical product to the gate of the other transistor.