Memory Array Write Timing With Delay-Locked Clock Alignment
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Solution Overview
Problem
As memory speeds increase, traditional methods for synchronizing write and system clock signals in memory systems fail to accommodate varying delays due to process, voltage, and temperature conditions, leading to mismatches that affect data and address signal alignment.
Innovation Solution
The implementation of a delay locked loop and mock delay blocks to synchronize write and system clock signals, ensuring they remain in sync despite different internal routing delays, using local and global clock tree mock delays to mimic and compensate for propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock delay matching is used to synchronize write and system clocks, then clock synchronization is achieved under nominal conditions, but synchronization fails under varying process, voltage, and temperature conditions
Solution Approach 1:
The patent implements a feedback mechanism where the actual delay of the system clock signal is measured and used to dynamically adjust the delay of the write clock signal. A delay measurement unit measures the delay of the system clock signal, and this measured delay value is fed back to a delay adjustment unit that adjusts the write clock delay accordingly, ensuring continuous synchronization under varying PVT conditions
Solution Approach 2:
The system automatically measures and adjusts its own clock delays without external intervention. The delay measurement unit and delay adjustment unit work together to self-correct synchronization issues by continuously monitoring and adjusting the write clock delay based on the actual system clock delay, making the system self-adapting to PVT variations
2Reliability
If write clock delay is increased to match system clock delay, then synchronization is achieved, but data signal storage requirements increase significantly
Solution Approach 1:
The patent performs preliminary measurement of the system clock delay and uses this information to pre-adjust the write clock delay, avoiding the need for large storage buffers. By measuring the delay in advance and compensating for it proactively, the system minimizes the storage requirements while maintaining synchronization
3Manufacturing precision
If fixed delay adjustment is applied to synchronize clocks, then nominal synchronization is achieved, but synchronization drifts under varying operating conditions
Solution Approach 1:
The patent transitions from fixed delay adjustment to dynamic delay adjustment. The delay measurement unit continuously monitors the system clock delay under varying operating conditions, and the delay adjustment unit dynamically adjusts the write clock delay in real-time, ensuring continuous synchronization despite changes in process, voltage, or temperature
Data Source
AI summary
Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.