Memory Command Decoding With Parallel EDC and Write Delay
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Solution Overview
Problem
Conventional memory systems face a bottleneck in command execution due to the sequential execution of error detection and correction (EDC) operations, which reduces data throughput and increases latency, especially with increasing clock speeds and complexity.
Innovation Solution
The method involves communicating commands and EDC data in parallel, allowing immediate execution of non-write operations while delaying write operations until EDC verification is complete, thereby reducing the impact of EDC operations on overall system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EDC operations are performed sequentially before command execution, then data integrity is ensured, but data throughput is reduced and execution latency increases
Solution Approach 1:
The EDC operation is performed in advance as a preliminary check on the command data before the actual command execution begins. The EDC unit calculates error detection codes for the command data and compares them with received codes, allowing the memory controller to proceed with command execution immediately while EDC verification completes in the background, thus ensuring data integrity without blocking throughput.
Solution Approach 2:
The patent separates the EDC verification process from the command execution timeline by implementing parallel processing dimensions. The EDC operation operates in a separate verification dimension that does not block the main command execution dimension, allowing both processes to occur simultaneously without interfering with each other's timing and performance characteristics.
2Measurement precision
If EDC operations are performed sequentially before command execution, then accurate data verification is achieved, but execution latency increases
Solution Approach 1:
The EDC verification is initiated as a preliminary action that runs concurrently with command execution rather than preceding it. The error detection code calculation and comparison begin immediately when command data arrives, completing in parallel with the command execution pipeline, thus maintaining verification accuracy while eliminating additional latency.
Solution Approach 2:
The EDC verification process maintains continuous operation alongside command execution without interruption or sequencing delays. The error detection and comparison operations continue uninterrupted in parallel with the command processing pipeline, ensuring that verification accuracy is maintained while preventing any pause or delay in command execution timing.
Data Source
AI summary
A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.