Memory Write Disturb Refresh Using Frequent-Write Identification
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Solution Overview
Problem
Conventional memory sub-systems fail to accurately identify frequently-written memory units, leading to write disturb effects that cause data corruption and increased error rates due to inefficient refresh operations based on predefined thresholds, which do not account for the actual aggressor memory units.
Innovation Solution
A memory sub-system that identifies frequently-written memory units using a majority identification algorithm, updating state information efficiently to perform refresh operations on adjacent units only when necessary, thereby accurately identifying and mitigating write disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed based on predefined thresholds, then memory units can be refreshed periodically, but write disturb effects cannot be accurately mitigated because the thresholds do not account for actual frequently-written memory units
Solution Approach 1:
The system implements feedback by monitoring write operations to memory units and using this information to dynamically adjust refresh operations. The controller tracks which memory units are frequently written and uses this feedback to target refresh operations specifically to adjacent memory units that are at risk of write disturb, rather than using fixed predefined thresholds.
Solution Approach 2:
The system performs preliminary identification of frequently-written memory units before write disturb occurs. By monitoring write patterns in advance and identifying aggressor memory units, the system can proactively refresh adjacent victim memory units before data corruption happens, rather than reacting after thresholds are exceeded.
2Reliability
If refresh operations are performed on all memory units, then data corruption can be prevented, but system throughput is reduced due to excessive refresh operations
Solution Approach 1:
The system applies local quality by targeting refresh operations only to specific memory units that need them - namely, the adjacent memory units next to frequently-written aggressor units. Instead of uniformly refreshing all memory units, the system identifies and refreshes only the local areas susceptible to write disturb, reducing overall refresh operations while maintaining data integrity where needed.
Solution Approach 2:
The system performs partial refresh action by refreshing only the necessary subset of memory units - specifically those adjacent to frequently-written units - rather than performing excessive refresh operations on all memory units. This partial action approach maintains sufficient data protection while reducing the overall burden on system throughput.
3Reliability
If frequently-written memory units are accurately identified, then write disturb effects can be mitigated, but additional monitoring and processing overhead is introduced
Solution Approach 1:
The system merges the identification of frequently-written memory units with the existing refresh operation framework. By integrating the monitoring function into the memory controller's existing operations and combining it with the refresh logic, the system avoids adding completely separate monitoring and processing systems, thereby reducing the overall complexity overhead.
Solution Approach 2:
The memory controller is designed with multi-functionality, serving both as the monitoring entity that tracks write operations and as the entity that executes refresh operations. This universal controller performs multiple functions - monitoring, identification, and refresh execution - within a single component, reducing the need for additional dedicated hardware or software modules.
Data Source
AI summary
A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units, the processing device is configured to maintain state information of the memory device in response to performing each write operation of a plurality of write operations on the memory device; identify, in view of the state information, a candidate memory unit of the plurality of memory units that has been written to by at least a threshold fraction of the plurality of write operations performed on the memory device; and responsive to determining that a number of write operations performed on the memory device satisfies a threshold refresh criterion and that one or more of the plurality of memory units that are proximate to the candidate memory unit satisfy a failed bit threshold criterion, refresh data stored at the one or more of the plurality of memory units that are proximate to the candidate memory unit.