Non-Volatile Memory Write Disturb Mitigation via Voltage Sequencing
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Solution Overview
Problem
Cross-point type non-volatile memory cell arrays experience write disturbance due to crosstalk, which existing methods fail to fully mitigate without the use of rectifying elements or complex voltage schemes.
Innovation Solution
A method and device configuration that includes memory cells with a variable resistive element and a rectifying element connected in series, where the bit lines and word lines are charged and discharged in a specific voltage sequence to minimize write disturbance, using a sense unit with controlled current paths and data processing circuits to manage write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cross-point type cell arrays are configured without rectifying elements to achieve high density, then memory density is improved, but write disturbance occurs due to crosstalk
Solution Approach 1:
The patent applies preliminary action by pre-charging non-selected bit lines to a voltage level that prevents write disturbance before the write operation begins. This preliminary voltage state ensures that when write voltages are applied to selected cells, the non-selected cells remain protected from crosstalk-induced writes, thus achieving high density without rectifying elements while preventing write disturbance.
2Object-affected harmful factors
If write-compensation voltage is applied to non-selected cells to mitigate crosstalk, then write disturbance is reduced, but device complexity increases
Solution Approach 1:
The patent employs parameter changes by utilizing the inherent voltage characteristics of the variable resistive elements and rectifying elements. By carefully selecting and controlling voltage levels (such as charging non-selected bit lines to specific voltages and applying write voltages within certain ranges), the patent achieves write disturbance mitigation through natural electrical behavior rather than complex active compensation circuits, thus reducing device complexity while maintaining effectiveness.
3Object-affected harmful factors
If rectifying elements are superposed on variable resistive elements to prevent crosstalk, then write disturbance is prevented, but manufacturing complexity increases
Solution Approach 1:
The patent applies merging by integrating the rectifying element and variable resistive element into a single unified memory cell structure. This combined structure allows both elements to coexist and function together within the same cell, enabling the benefits of write disturbance prevention while maintaining a compact design that is compatible with standard cross-point array fabrication processes, thus improving ease of manufacture compared to separate implementations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces write disturbance in non-volatile memory devices by ensuring that only the selected memory cell receives the write voltage, thereby preventing incorrect writes or erases in non-selected cells, while allowing for high-density memory cell arrays without the need for additional rectifying elements.
Implementation Method 1
The variable resistive elements are known to have two types of operational modes. One operational mode involves switching between a high-resistance state and a low-resistance state by changing polarity of the applied voltage, which is referred to as 'bipolar type'. The other involves switching between a high-resistance state and a low-resistance state by controlling values and application time of voltage without changing polarity of the applied voltage, which is referred to as 'unipolar type' (or 'non-polar type').
Implementation Method 2
a rectifying element such as a diode may be superposed on a variable resistive element
Data Source
AI summary
The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.