Nonvolatile Memory Write Circuit Mitigating Cell Disturbance
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Solution Overview
Problem
Next-generation nonvolatile memory apparatuses face challenges in efficiently performing write operations without disturbing adjacent memory cells, particularly due to the inability to distinguish and prevent voltage and current application to defective cells, leading to unnecessary current consumption and increased disturbance risks.
Innovation Solution
The nonvolatile memory apparatus incorporates a write circuit and sense amplifier to perform a preselection operation, determining whether a memory cell has snapped back, and selectively applies reset or set write operations based on the cell's state, thereby interrupting voltage and current to unsnapped cells to prevent disturbances and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage and current are applied to all selected memory cells during write operation, then write speed is improved, but disturbance to adjacent memory cells increases and power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different memory cells based on their snap-back status. Snapped-back cells receive full write voltage while unsnapped cells receive reduced or zero voltage, creating localized quality differences that prevent disturbance to cells that don't need writing.
Solution Approach 2:
The patent performs a preliminary preselection operation before the actual write operation to identify which memory cells have snapped back. This preliminary action allows the system to prepare appropriate voltage levels for each cell before applying write voltage, preventing disturbance to unsnapped cells.
2Reliability
If voltage and current are applied to all selected memory cells during write operation, then write operation completeness is improved, but power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different memory cells based on their snap-back status. Snapped-back cells receive full write voltage while unsnapped cells receive reduced or zero voltage, creating localized quality differences that prevent disturbance to cells that don't need writing.
Solution Approach 2:
The patent applies write voltage only to the subset of memory cells that have snapped back rather than all selected cells. This partial action reduces power consumption while maintaining write operation completeness for the cells that actually require writing.
3Object-affected harmful factors
If preselection operation is performed to identify snapped-back cells, then disturbance to unsnapped cells is reduced, but device complexity increases
Solution Approach 1:
The patent uses the memory cells themselves to indicate their snap-back status through their electrical characteristics during the preselection operation. The cells self-identify their state through their response to the preselection voltage, eliminating the need for external sensing circuits or additional complexity.
Solution Approach 2:
The patent combines the preselection operation and write operation into a single integrated process. The preselection voltage application and subsequent write voltage application are merged in time and control, reducing the need for separate control circuits and reducing overall device complexity.
Data Source
AI summary
A nonvolatile memory apparatus may include a write circuit and a sense amplifier. The write circuit may perform a preselection operation on a selected memory cell. When the selected memory cell was snapped back, the write circuit may selectively perform a reset write operation and a set write operation on the selected memory cell according to write data. When the selected memory cell is not snapped back, the write circuit may apply no voltage and no current to the selected memory cell. The sense amplifier may sense whether the selected memory cell was snapped back.