Memory Write Path With Independent DM Flag and ECC Correction
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Solution Overview
Problem
Current memory systems face challenges in optimizing area, power consumption, and operating time due to the limitations of existing ECC, DBI, and DM unit operations, particularly in parallel operation and power efficiency.
Innovation Solution
A memory system and method that includes an ECC unit for error correction, a DBI unit for data inversion, and a DM unit that operates independently to minimize high logic bits, reducing power consumption and latency by generating flags based on data patterns and error corrections, allowing the DM unit to function regardless of single error occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DM unit operates dependent on the ECC unit to receive corrected data, then the accuracy of DM flag generation is improved, but the operating time and latency of the memory system increases
Solution Approach 1:
The DM unit performs preliminary action by generating the DM flag directly from received data before the ECC unit completes error correction. This allows the DM flag generation to proceed in parallel with the ECC correction process, reducing overall latency while maintaining accuracy through subsequent synchronization with the corrected data.
Solution Approach 2:
The memory system is segmented into independent operational paths: the DM unit operates on received data independently from the ECC correction path. This segmentation allows parallel processing where the DM flag generation does not wait for ECC completion, reducing operating time while accuracy is maintained through the synchronization mechanism that combines DM and ECC results.
2Productivity
If the DM unit operates independently of the ECC unit, then the operating time and system latency are reduced, but the reliability of data integrity may be compromised
Solution Approach 1:
The system implements feedback by synchronizing the independently generated DM flag with the ECC corrected data. The DM unit operates independently on received data while the ECC unit processes error correction, and their results are combined through feedback mechanisms that ensure the final output reflects both the DM pattern detection and ECC error correction, maintaining data integrity while achieving parallel processing speedups.
3Ease of operation
If all bits are written to memory without masking, then the simplicity of the write operation is maintained, but the power consumption increases due to unnecessary write operations
Solution Approach 1:
The write operation applies local quality by selectively masking individual data groups based on their specific DM flag status. Instead of uniformly writing or not writing all data, the system evaluates each data group's DM flag independently and applies masking only where needed, optimizing power consumption while maintaining operational simplicity through a standardized masking mechanism.
4Reliability
If the masking value is set to the data masking pattern boundary value, then the reliability of error detection is improved, but the number of high logic bits increases leading to higher power consumption
Solution Approach 1:
The system applies parameter changes by optimizing the masking value to balance between error detection reliability and power consumption. Rather than using the maximum boundary value, the masking value is tuned to provide sufficient error detection capability while minimizing the number of high logic bits generated, thereby reducing power consumption while maintaining adequate reliability for the application.
Data Source
AI summary
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.