Memory Write Path With Independent DM Flags for Lower Latency
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Solution Overview
Problem
Current memory systems face challenges in optimizing area, power consumption, and operating time due to the need for efficient operation of ECC, DBI, and DM units, particularly in high-speed and high-capacity semiconductor devices like DRAM, where existing DM units cannot operate independently of ECC units, leading to increased latency and power consumption.
Innovation Solution
A memory system that includes an ECC unit for error correction, a DBI unit for data inversion, and a DM unit that operates independently to minimize high logic bits, reducing power consumption and latency by generating DM flags based on the number of high logic bits in data groups, allowing the DM unit to function regardless of error corrections performed by the ECC unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DM unit operates dependent on the ECC unit, then error correction reliability is improved, but operating time and system complexity increase
Solution Approach 1:
The patent segments the error handling functionality by separating the DM (Data Masking) unit from the ECC (Error Correction Code) unit. The DM unit independently generates masking flags based on data patterns without waiting for ECC processing, while the ECC unit handles actual error correction. This segmentation allows parallel operation of data masking and error correction functions, reducing overall operating time while maintaining reliability through dedicated error correction capability.
Solution Approach 2:
The DM unit performs preliminary data masking operations before ECC processing completes. By generating masking flags independently and in advance based on data patterns (such as all-zero or all-one patterns), the system prepares data for potential masking without waiting for the ECC unit to finish its error correction analysis, thereby reducing critical path latency.
2Loss of time
If the DM unit operates independently, then operating time is reduced, but coordination complexity between units increases
Solution Approach 1:
The patent introduces a coordination mechanism where the DM unit's independent operation is mediated through shared control signals and status flags with the ECC unit. The DM unit generates masking flags independently, but these flags are coordinated with ECC status to determine final data output. This intermediary coordination approach allows independent operation for speed while managing complexity through standardized interface protocols.
3Use of energy by moving object
If data masking is applied to minimize high logic bits, then power consumption is reduced, but data accuracy may be affected
Solution Approach 1:
The patent applies data masking selectively rather than uniformly across all data. The DM unit analyzes data patterns and applies masking flags only to specific data groups that exhibit high logic bit patterns (such as consecutive high logic bits). This local quality approach minimizes power consumption for problematic data segments while leaving other data segments unchanged, thereby maintaining data accuracy where masking is not applied.
Solution Approach 2:
The system dynamically changes the masking parameter based on detected data patterns. When high logic bit patterns are detected (indicating potential power consumption issues), masking is applied; when patterns are already optimized, masking is bypassed. This parameter-based dynamic control balances power reduction with data integrity by adapting masking application to actual data characteristics.
Data Source
AI summary
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.