Memory Write Timing Control With Threshold-Based DQS Training
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Solution Overview
Problem
The Un-matched DQS architecture in memory systems requires frequent training operations due to temperature changes, leading to performance degradation and inefficiencies in data transfer.
Innovation Solution
A memory system that includes a controller and memory chip with a delay circuit in the data strobe signal path, where the controller performs a latch test operation to determine the number of error bits and adjusts the delay circuit only when the error exceeds a threshold, thereby skipping unnecessary training operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If training operations are performed frequently to maintain data transfer accuracy under temperature changes, then data transfer reliability is improved, but system productivity deteriorates due to performance degradation and transfer time loss
Solution Approach 1:
The patent applies partial action by performing training operations selectively rather than continuously. The controller executes training operations only when error bits exceed a threshold value, performing partial training actions instead of excessive frequent training, thereby balancing reliability maintenance with productivity preservation
Solution Approach 2:
The patent implements feedback mechanisms where the controller monitors error bits in latched data and uses this feedback to determine whether training operations are needed. The latch test operation provides feedback about timing accuracy, and this feedback controls the frequency of subsequent training operations, creating a closed-loop system that maintains reliability while minimizing productivity loss
2Measurement precision
If training operations are executed at high frequency to compensate for delay circuit changes, then timing accuracy is improved, but data transfer speed deteriorates
Solution Approach 1:
The patent uses partial action by executing training operations only when necessary (when error bits > threshold) rather than continuously. This partial execution maintains timing accuracy when needed while preserving data transfer speed during normal operation, resolving the contradiction between measurement precision and speed
3Reliability
If delay circuit adjustment is performed continuously to maintain optimal timing, then latching reliability is improved, but system complexity and operation time increase
Solution Approach 1:
The patent applies partial action by performing delay circuit adjustment (training operation) only when error detection indicates it is necessary. This selective approach maintains latching reliability when timing drift occurs while avoiding unnecessary operations that would increase system complexity and operation time
Solution Approach 2:
The system performs self-diagnosis through latch test operations that detect timing errors automatically. When errors are detected, the system self-corrects by executing training operations to adjust the delay circuit, eliminating the need for continuous external intervention or complex control mechanisms
Data Source
AI summary
According to one embodiment, in a first write operation, a controller transfers first data to be written to a memory device and causes the memory device to store first data into a memory cell array. In a second write operation, the controller transfers second data to be written to the memory device and acquires the second data from a buffer circuit. The controller determines the number of error bits included in the acquired second data. When the number of error bits is larger than a first threshold value, the controller executes a training operation of adjusting delay time of a delay circuit. When the number of error bits is smaller than the first threshold value, the controller causes the memory device to store, into the memory cell array, the second data having been stored in the buffer circuit, without executing the training operation.