Memory Device Write Driver Gate Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face challenges in efficiently generating and adjusting write voltages with reduced area and power consumption, especially as power supply voltages decrease, leading to instability and voltage headroom issues during write operations.
Innovation Solution
A memory device architecture that includes a memory cell array, row and column decoders, write drivers, and control logic with a charge pump and reference resistance element, allowing for the generation of a gate voltage higher than the write voltage, which is used to quickly adjust and recover write voltages, and an operating method that adjusts resistance values and charge pump capacity to secure necessary write voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a memory device uses a conventional write voltage generation circuit, then the area occupied by the write voltage generation circuit is large and power consumption is high, but the write voltage adjustment and recovery speed is slow
Solution Approach 1:
The patent changes the operating parameters of the write driver transistors by applying a gate voltage that is higher than the write voltage itself. This parameter change enables the transistors to operate in a region that provides both fast switching speed and reduced voltage headroom requirements, thereby achieving fast voltage adjustment and recovery while minimizing circuit area
Solution Approach 2:
The patent employs dynamic control of the gate voltage to the write driver transistors. By dynamically adjusting the gate voltage during write operations and recovery phases, the system achieves rapid transition between states, improving the adjustment and recovery speed without requiring oversized circuit components
2Reliability
If a memory device uses a conventional write voltage generation circuit, then the area occupied by the write voltage generation circuit is large and power consumption is high, but the write operation stability is insufficient
Solution Approach 1:
The patent changes the gate voltage parameter to be higher than the write voltage, which stabilizes the write driver transistor operation by ensuring adequate overdrive voltage during write operations. This parameter change improves reliability while the high-speed operation reduces power consumption compared to conventional slower circuits
3Use of energy by stationary object
If the power supply voltage decreases to reduce power consumption, then power consumption is reduced, but the write voltage level becomes insufficient
Solution Approach 1:
The patent employs dynamic boosting of the gate voltage to levels higher than the write voltage during critical operations. This dynamic approach allows the system to maintain adequate write voltage levels even when the overall power supply voltage is reduced, enabling low-power operation without sacrificing write capability
Solution Approach 2:
By changing the gate voltage parameter to exceed the write voltage level, the patent creates voltage headroom that compensates for reduced power supply voltage. This parameter change ensures that sufficient write voltage is achieved even in low-power supply conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster and more stable write operations with reduced area and power consumption, addressing voltage headroom issues and ensuring a higher write voltage level, even at lower power supply voltages.
Implementation Method 1
a charge pump that generates the gate voltage in response to a third enable signal
Implementation Method 2
a reference resistance element that is connected between a comparison node and a ground node
Data Source
AI summary
A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.