Memory Write Driver Voltage Level Shifting and Bit Line Isolation
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Solution Overview
Problem
Existing memory circuit write drivers face challenges in level shifting voltages from a lower voltage domain to a higher domain for writing data, while minimizing interference with bit lines during both write and read operations, and ensuring isolation during non-writing intervals.
Innovation Solution
The proposed solution involves a control circuit that operates first and second push-pull drivers to generate drive signals in a higher voltage domain based on an input signal, with mode select signals determining the logic levels and floating nodes during non-writing modes, utilizing p-channel and n-channel FETs to isolate the drivers from bit lines when not writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a write driver is configured to level shift voltages from a lower voltage domain to a higher voltage domain for writing data to memory cells, then data writing capability is improved, but the complexity of the write driver increases
Solution Approach 1:
The patent introduces a control circuit as an intermediary component between the lower voltage domain circuitry and the higher voltage domain memory cells. This control circuit includes level shifting circuitry that mediates voltage conversion and signal routing, allowing the write driver to operate in a lower voltage domain while still being able to write to higher voltage domain memory cells without directly increasing the complexity of the write driver itself
Solution Approach 2:
The control circuit is designed to perform multiple functions: it acts as a level shifter, a signal router, and a mode controller. By making this single component multi-functional, the patent avoids distributing complexity across multiple separate components, thereby managing the overall system complexity while achieving voltage domain adaptability
2Productivity
If the write driver generates drive signals on bit lines during write operations, then data writing is enabled, but interference with read operations occurs
Solution Approach 1:
The patent implements periodic action through mode-selective operation. The control circuit is configured to enable write operations only during specific time periods when no read operations are occurring. By alternating between write and read modes in a periodic fashion, the system achieves high data writing throughput while preventing interference with read operations, as the write driver remains inactive during read cycles
Solution Approach 2:
The write driver is made dynamic through mode-selective activation. The control circuit dynamically adjusts the state of the write driver based on the current operation mode (write or read). During read operations, the write driver is turned off or isolated, while during write operations, it becomes active. This dynamic behavior allows the system to achieve both high writing productivity and minimal interference with reading
3Duration of action of stationary object
If the write driver remains active during non-writing intervals, then continuous operation is maintained, but isolation from bit lines is compromised
Solution Approach 1:
The control circuit implements periodic inactivity during non-writing intervals. Instead of continuous operation, the write driver is periodically activated only during write operations and left in a high-impedance or inactive state during read and idle periods. This periodic action pattern ensures reliable isolation from the bit lines during non-writing intervals while maintaining operational capability when needed
Data Source
AI summary
A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.