Memory System Write Driver for Simultaneous Cell Writes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in reducing write latency and improving write operation speed, particularly in next-generation memory apparatuses that require high integration, non-volatility, and low power consumption, such as phase-change RAM (PRAM), nano floating gate memory (FTGM), polymer RAM (PoRAM), magnetic RAM (MRAM), and ferroelectric RAM (FeRAM).
Innovation Solution
A memory system design that includes a write driver capable of increasing write current based on a simultaneous write control signal, allowing simultaneous write operations on multiple memory cells sharing a bit line, thereby reducing write latency and enhancing write operation speed. This is achieved through a write driver configuration with a voltage supply terminal, parallel current sources, and a switching element that doubles the write current when specific conditions are met, ensuring efficient data writing in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If simultaneous write operations are performed on multiple memory cells sharing a bit line, then write operation speed is improved, but write current requirement increases
Solution Approach 1:
The write driver dynamically adjusts the write current based on the write mode. When simultaneous write operations are detected (first write mode), the write driver activates additional current sources to provide increased write current. When single memory cell write operations are performed (second write mode), the write driver uses normal write current, thereby adapting the power consumption to the operational requirements.
Solution Approach 2:
The patent changes the electrical parameter (write current magnitude) based on the operation mode. The write driver switches between two current levels: a higher current level for simultaneous write operations to multiple memory cells, and a lower current level for single memory cell writes, optimizing both speed and power consumption according to the specific write operation required.
2Loss of time
If write current is increased for simultaneous write operations, then write latency is reduced, but power consumption increases
Solution Approach 1:
The write driver dynamically switches between different current consumption states based on the write operation type. For simultaneous write operations targeting multiple memory cells on the same bit line, the system activates high current mode to reduce write latency. For single memory cell writes, the system operates in low current mode, thereby minimizing power consumption while maintaining acceptable write performance.
Solution Approach 2:
The system adjusts the write current parameter adaptively: using elevated current levels only when simultaneous writes are performed (reducing latency for batch operations), and returning to standard current levels for individual writes (conserving energy). This conditional parameter adjustment resolves the trade-off between write latency and power consumption.
3Use of energy by moving object
If normal write current is used for all write operations, then power consumption is reduced, but write operation speed decreases for multiple memory cells
Solution Approach 1:
The write driver implements dynamic current adjustment based on operational context. When the control logic detects that multiple memory cells on the same bit line require simultaneous writes, the write driver transitions to high-current mode to maintain fast write speeds. When only single memory cell writes are needed, the write driver operates in low-current mode, optimizing power efficiency for lightworkloads.
4Speed
If write driver always operates at high current level, then write operation speed is maintained, but power consumption increases for all operations
Solution Approach 1:
The write driver operates dynamically rather than statically at a fixed current level. It continuously monitors write command parameters and adjusts its output current accordingly, switching between high and low current modes based on whether simultaneous writes are required. This dynamic operation maintains high write speeds when needed while minimizing power consumption during normal single-cell write operations.
Solution Approach 2:
The write current parameter is changed adaptively based on the write operation type. The system uses high current values only for simultaneous write operations to multiple memory cells, and low current values for single memory cell writes, thereby optimizing the balance between write speed and power consumption across different operational scenarios.
Data Source
AI summary
A memory system includes a memory apparatus including a write driver and a memory controller configured to control the memory apparatuses. The memory controller includes a command comparison circuit configured to compare word line addresses, bit line addresses, and pieces of write data of a first write command and a second write command and output a simultaneous write control signal having a first level when the bit line addresses and the pieces of write data are the same as each other and most significant bits (MSBs) of the word line addresses are different from each other and a processor configured to transfer a simultaneous write command for simultaneously operating the first write command and the second write command to the memory apparatus when the simultaneous write control signal having the first level is output from the command comparison circuit.