Memory Write Circuit for Pattern Writes With ECC and Data Inversion
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently performing pattern write operations while minimizing layout area and power consumption, as they require separate design changes for error correction, data inversion, and data masking operations during pattern writes.
Innovation Solution
The semiconductor device incorporates a selection input circuit and a core data generation circuit that generate selection data, selection parity, and selection data control signals during write operations. These signals are set to predetermined logic levels during pattern write operations, allowing existing error correction, data inversion, and data masking circuits to be used without design changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate design changes are made for error correction, data inversion, and data masking operations during pattern writes, then operational functionality is improved, but layout area and power consumption increase
Solution Approach 1:
The selection input circuit is designed to perform multiple functions (error correction, data inversion, data masking) through a single unified structure that generates selection data, selection parity, and selection data control signals. These signals are set to predetermined logic levels during pattern write operations, allowing existing circuits to handle multiple operations without requiring separate design changes for each function.
2Adaptability or versatility
If separate design changes are made for error correction, data inversion, and data masking operations during pattern writes, then operational functionality is improved, but power consumption increases
Solution Approach 1:
The selection input circuit serves as a universal control unit that manages error correction, data inversion, and data masking operations through unified signal generation. By setting selection data, selection parity, and selection data control signals to predetermined logic levels during pattern writes, the design eliminates the need for separate power-consuming circuits for each operation.
Solution Approach 2:
Multiple operational functions (error correction, data inversion, data masking) are merged into a single selection input circuit that generates all necessary control signals. This consolidation reduces the total power consumption compared to having separate dedicated circuits for each function.
3Area of stationary object
If existing circuits are used without design changes for pattern write operations, then layout area and power consumption are reduced, but operational flexibility may be limited
Solution Approach 1:
The selection input circuit changes the logic levels of selection data, selection parity, and selection data control signals to predetermined values during pattern write operations. This parameter change allows existing circuits to support multiple operations (pattern writes, error correction, data inversion, data masking) without physical redesign, maintaining both area efficiency and operational flexibility.
Data Source
AI summary
A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.