Memory Write Circuit Reuse for ECC Pattern Write Operations

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Solution Overview

Problem

Semiconductor devices face challenges in efficiently performing pattern write operations due to limitations in error correction and data inversion operations during write operations, which affect data storage and retrieval processes.

Innovation Solution

The semiconductor device incorporates a selection input circuit and a core data generation circuit that generate selection data, selection parity, and selection data control signals to set predetermined logic levels during pattern write operations, enabling error correction and data inversion without design changes to existing error correction and data masking circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If existing error correction and data masking circuits are used for pattern write operations, then device complexity is reduced, but the circuits must be modified to handle pattern write operations correctly

Engineering Contradiction:

Improvecircuit design complexityVSAvoidcircuit modification requirement

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The selection input circuit is designed to perform multiple functions: during normal write operations it processes actual data through error correction and masking circuits, while during pattern write operations it generates predetermined logic levels. This multi-functionality allows the same circuit architecture to handle both operation types without requiring separate dedicated circuits for pattern writes, thereby reducing overall device complexity while avoiding extensive modifications to existing circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The selection input circuit dynamically switches between two operational modes based on the operation type. During normal write operations, it passes through actual data; during pattern write operations, it generates predetermined logic levels. This dynamic behavior allows the circuit to adapt its function based on operational context, enabling the use of existing error correction and masking circuits for both operation types without requiring permanent structural modifications.

Inventive Principle:

Principle #15Dynamics

2Reliability

If pattern write operations use dedicated circuits, then operation reliability is improved, but layout area and power consumption increase

Engineering Contradiction:

Improvepattern write operation reliabilityVSAvoidlayout area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The selection input circuit serves as a universal interface that handles both normal write operations and pattern write operations. During pattern write operations, it generates predetermined logic levels that are then processed by the existing error correction and masking circuits, ensuring reliable operation without requiring dedicated pattern write circuits. This approach maintains reliability while avoiding the layout area increase that would result from adding separate dedicated circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the pattern write functionality into the existing write operation infrastructure by using the selection input circuit to generate predetermined logic levels that are then processed by the same error correction and masking circuits used for normal writes. This consolidation eliminates the need for separate pattern write circuits, thereby maintaining reliability while reducing layout area.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If pattern write operations use dedicated circuits, then operation reliability is improved, but power consumption increases

Engineering Contradiction:

Improvepattern write operation reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The selection input circuit functions as a universal interface that handles both normal and pattern write operations. During pattern write operations, it generates predetermined logic levels that are then processed by the existing error correction and masking circuits, ensuring reliable operation without requiring dedicated pattern write circuits that would consume additional power. This approach maintains reliability while minimizing power consumption by reusing existing circuitry.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines pattern write functionality with the existing write operation infrastructure. The selection input circuit generates predetermined logic levels during pattern writes, which are then processed by the same error correction and masking circuits used for normal writes. This merging eliminates the need for separate power-consuming pattern write circuits while maintaining operational reliability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11409598B2Semiconductor devices

Publication Date: 2022.08.09 SK HYNIX INC

AI summary

A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.