Memory Device Write Error Check Circuit for Data Integrity
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Solution Overview
Problem
As memory device density increases, it becomes increasingly difficult to fabricate error-free memory devices, and existing error correction methods are inadequate in efficiently correcting errors during data transmission in memory systems.
Innovation Solution
Incorporating a write error check circuit in memory devices to detect errors using error correction codes during write operations and storing data and error correction codes when no errors are detected, with an error correction circuit in the memory controller to correct errors in data transferred from the memory device using error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device density is increased to improve storage capacity, then storage capacity is improved, but manufacturing precision deteriorates making it difficult to fabricate error-free memory devices
Solution Approach 1:
The patent applies preliminary action by performing error detection and correction before data is written to the memory device. The memory controller generates error correction codes for write data and transmits them to the memory device along with the data. The memory device detects errors in the received data using the error correction codes before storing, preventing corrupted data from being written to the memory array. This proactive error handling allows higher density memory devices to maintain data integrity despite increased manufacturing difficulties.
2Reliability
If error correction codes are used to correct errors in data transmitted in memory systems, then data reliability is improved, but device complexity increases due to additional error correction circuits
Solution Approach 1:
The patent merges error correction functionality into the memory device itself rather than requiring separate external error correction systems. The memory device includes integrated error detection and correction circuits that work with the error correction codes generated by the memory controller. This integration consolidates error handling functions within the memory subsystem, improving data reliability while managing complexity through unified design rather than separate components.
Solution Approach 2:
The patent uses error correction codes as an intermediary mechanism between the memory controller and memory device. These codes act as a mediator that carries error detection and correction information along with the data, enabling reliable error correction without requiring complex direct communication or additional hardware interfaces between components.
3Reliability
If write error detection is performed using error correction codes during write operations, then data reliability is improved, but processing time increases due to additional error checking steps
Solution Approach 1:
The patent performs error detection using error correction codes during the write operation itself, before data is committed to the memory array. This preliminary error checking ensures that only valid data is written, improving reliability. The error detection is integrated into the write path rather than being a separate post-processing step, which helps minimize the time penalty by combining error checking with the existing write operation flow.
Data Source
AI summary
A memory device includes a write error check circuit suitable for detecting an error in received data using an error correction code during a write operation; and a memory core suitable for storing the received data and the received error correction code when no error is detected by the write error check circuit.