Memory Write Leveling Circuit for CWL-DQS Edge Alignment
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Solution Overview
Problem
The inconsistency in time specifications between the Column Address Strobe Write Latency (CWL) and its shortened time during internal write leveling in memories, particularly in memory systems with fly-by bus topology, prevents accurate alignment of write signals, leading to inefficiencies in data storage.
Innovation Solution
A write leveling circuit with a write signal generation unit and sampling unit that adjusts write signals based on indication signals indicating odd or even multiples of clock cycles, ensuring alignment of effective edges through controlled delay mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the write signal is delayed based on the shortened CWL to achieve internal write leveling, then the write leveling process is improved, but the time specifications of the CWL and shortened CWL become inconsistent, making it unable to directly determine the indication signal
Solution Approach 1:
The patent introduces a parity bit as an intermediary element to bridge the inconsistency between CWL and shortened CWL specifications. The parity bit serves as a mediator that enables the system to determine the correct indication signal despite the specification inconsistency, allowing the write leveling process to proceed accurately.
Solution Approach 2:
The patent modifies the indication signal by adding a parity bit parameter to handle the time specification inconsistency. This parameter change allows the system to distinguish between different CWL scenarios (even vs. odd multiples) and correctly determine the write signal delay requirement, resolving the contradiction between productivity improvement and specification consistency.
2Productivity
If the effective edge alignment between DQS and write signal is not achieved, then data storage efficiency is reduced, but continuous adjustment of delay time increases system complexity
Solution Approach 1:
The patent implements a feedback mechanism where the sampling unit continuously monitors the alignment between the DQS effective edge and the write signal effective edge. Based on this feedback, the system automatically adjusts the delay time to achieve proper alignment, ensuring data storage efficiency without requiring complex manual intervention.
Solution Approach 2:
The write leveling circuit performs self-adjustment by using the sampling unit to detect alignment status and automatically modifying the delay time accordingly. This self-service capability allows the system to achieve and maintain optimal data storage efficiency while keeping the adjustment mechanism relatively simple and automated.
Data Source
AI summary
A write leveling circuit applied to a memory includes a write signal generation unit and a sampling unit. The write signal generation unit is configured to receive a first clock signal and a first indication signal, and delay a first write signal according to the first clock signal, the first indication signal and a specified bit in the first indication signal, and output a second write signal. The sampling unit is connected to the write signal generation unit, and configured to receive a first data strobe signal and the second write signal, and output a second sampling signal according to received first Data Strobe Signal (DQS) and the second write signal.