Memory Write Leveling Using Multi-Point DQS Timing Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face challenges in accurately receiving signals at the correct timing due to increased communication frequencies, which can impair reliability.
Innovation Solution
A memory device design that includes a command decoder, data strobe signal path, and write circuits to synchronize and align signal timings through external and location-selective internal write leveling operations, enhancing reliability by adjusting signal timings at multiple locations within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the signal used for communication with a host device is increased to meet demand for higher communication speeds, then communication speed is improved, but the memory device's ability to accurately receive signals at the correct timing is impaired, reducing communication reliability
Solution Approach 1:
The patent performs a write leveling operation before normal write operations to pre-align the timing between clock signals and data strobe signals. The command decoder generates a write leveling pulse signal that is sampled by write circuits at multiple locations to determine optimal timing offsets, which are then stored and applied during subsequent communications. This preliminary timing calibration ensures that when high-frequency communication begins, the signals are already synchronized, preventing timing errors that would otherwise occur at higher frequencies.
Solution Approach 2:
The patent dynamically adjusts timing parameters (phase offsets between clock and data strobe signals) based on the operating frequency. At different communication frequencies, the optimal timing alignment differs, so the system changes the timing parameters adaptively. The write leveling operation measures the actual signal arrival times and adjusts the phase relationship between clock and data strobe signals to compensate for frequency-dependent timing variations, maintaining reliable communication across different speed settings.
2Device complexity
If write leveling operation uses single location sampling, then device complexity is reduced, but measurement precision of signal timing alignment is insufficient
Solution Approach 1:
The patent divides the timing measurement process into multiple segments by sampling the write leveling pulse signal at multiple different locations within the memory device. Each location corresponds to a different stage in the signal processing path, allowing the system to measure timing offsets at various points. This segmented approach captures the cumulative timing variations across different signal paths, providing comprehensive timing information without requiring a single overly complex measurement system.
Solution Approach 2:
The patent combines the timing measurements from multiple locations to determine the overall optimal timing alignment. The write circuits at different locations each provide timing data, and these measurements are merged to establish the final phase offset settings. By combining multiple simpler measurements from different points in the system, the patent achieves high measurement precision equivalent to what would require a single complex measurement system, while keeping individual circuit elements simpler.
Data Source
AI summary
A memory device including: a command decoder to receive a write command signal in synchronization with a clock signal and generate a write leveling pulse signal in response to the write command signal and in synchronization with the clock signal in a write leveling operation; a first write circuit to receive a first data strobe signal at a first location on a data strobe signal path, first sample the write leveling pulse signal in synchronization with the first data strobe signal in the write leveling operation, and output a first write leveling signal; and a second write circuit to receive a second data strobe signal at a second location on the data strobe signal path, second sample the write leveling pulse signal in synchronization with the second data strobe signal in the write leveling operation, and output a second write leveling signal.