Memory Device Testing With Identity-Based Write Leveling
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Solution Overview
Problem
The increasing density of memory device circuits leads to higher error rates and fabrication issues, necessitating effective testing methods to confirm product reliability and yield.
Innovation Solution
A system and method involving a tester that generates multi-purpose commands and data signals to store identities in mode registers, performs write leveling operations, and compares write and read data to determine test results, allowing for precise setting of time shifts in write leveling pulses based on individual memory device identities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory devices are designed with higher circuit density to reduce size, then manufacturing cost and device size are improved, but error rates and fabrication issues increase
Solution Approach 1:
The patent applies preliminary action by performing write leveling training operations before actual memory operations to determine optimal setting values. The tester conducts training writes and reads to measure write leveling pulse timings, then stores these measured values in mode registers before normal operation begins. This preliminary calibration compensates for process variations and reduces errors in high-density memory devices.
Solution Approach 2:
The patent changes the parameter of write leveling pulse timing by measuring actual pulse timings during training operations and storing these measured values as setting values. The system adjusts write leveling pulse parameters based on individual device characteristics, allowing optimization of timing parameters to compensate for fabrication variations in high-density circuits.
2Reliability
If individualized setting values are applied to each memory device to improve reliability, then test performance and product quality are improved, but testing time and complexity increase
Solution Approach 1:
The patent merges multiple operations into a single training sequence. The tester performs training writes, training reads, and write leveling measurements all in one integrated operation rather than separate steps. Multiple memory devices are tested simultaneously using the same training sequence, reducing overall testing time while still determining individual setting values for each device.
Solution Approach 2:
The memory devices perform self-characterization during the training operation. Each device automatically generates its own write leveling pulse timings and provides feedback through training read operations, allowing the tester to extract individual setting values without requiring complex external measurement equipment or manual adjustment for each device.
3Manufacturing precision
If write leveling training operations are performed to determine setting values, then manufacturing precision is improved, but productivity decreases due to additional testing steps
Solution Approach 1:
The patent makes the training operation multi-functional by using the same training sequence to accomplish multiple objectives: verifying basic memory functionality, measuring write leveling pulse timings, and determining optimal setting values. This eliminates the need for separate functionality verification steps and integrates precision measurement into the standard testing workflow.
Solution Approach 2:
The training operation maintains continuous useful action by performing measurements and storing setting values without interrupting the normal testing flow. The training writes and reads are integrated into the standard memory test sequence, and setting values are stored in mode registers during normal operation rather than requiring separate calibration steps that would halt production.
Data Source
AI summary
A system including memory devices and a tester is provided. The tester is configured to: generate a first multi-purpose command to the memory devices and a first data signal to each of a first group in the memory devices to store a first identity; generate a second multi-purpose command to the memory devices and the first data signal to each of a second group in the memory devices to store a second identity; generate a third multi-purpose command and a fourth multi-purpose command to the memory devices to select the first and second groups in the memory devices to have first and second time shifts in write leveling pulses therein separately; transmit a write datum to the memory devices for performing a write operation to the memory devices; and receive read data and compare the write datum and the read data for a test result.