Memory Write Leveling Test Using Grouped Pulse Shift Training
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Solution Overview
Problem
The increasing density of memory device circuits leads to higher error rates and fabrication issues, necessitating effective testing methods to confirm product reliability and yield.
Innovation Solution
A system and method involving a tester that generates multi-purpose commands and data signals to store identities in mode registers of memory devices, performs write leveling operations, and compares write and read data to determine test results, allowing for efficient defect detection and setting optimal write leveling pulse shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory device circuits are designed with higher density to reduce size and improve speed, then manufacturing precision and reliability deteriorate due to increased errors and fabrication issues
Solution Approach 1:
The patent applies preliminary action by performing write leveling training operations before actual data writing to determine optimal write leveling pulse shifts. The tester conducts training writes, reads back the data, compares results, and determines setting values in advance. This preliminary characterization ensures that when high-density memory devices operate at higher speeds, the pre-determined optimal timing parameters compensate for fabrication variations, maintaining reliability despite increased circuit density.
2Measurement precision
If individual write leveling pulse shifts are optimized for each memory device group, then test precision and reliability improve, but device complexity and test time increase due to multiple training operations
Solution Approach 1:
The patent segments memory devices into multiple groups based on their write leveling characteristics. Instead of testing each device individually, the tester performs training operations on groups of devices with similar characteristics, determining a common optimal write leveling pulse shift for each group. This segmentation approach maintains measurement precision by accounting for device variations while significantly reducing test time compared to individual device testing.
Solution Approach 2:
The patent merges multiple training operations into a single efficient process by combining the training writes and reads for multiple device groups. The tester executes training operations, reads data from multiple groups simultaneously, compares results, and determines setting values in a unified workflow. This merging eliminates redundant operations and reduces overall test time while maintaining the precision of individual group optimization.
3Productivity
If multi-purpose commands are used to store identities and perform write leveling operations, then device versatility and test efficiency improve, but device complexity increases due to additional mode registers and command sequences
Solution Approach 1:
The patent implements universality by using multi-purpose commands that serve dual functions: storing device identities in mode registers and performing write leveling operations. The same command interface is used for both characterization and operational configuration. This multi-functionality improves test efficiency by eliminating the need for separate command sequences while the added complexity is managed through a unified, standardized command structure that simplifies the overall testing workflow.
Data Source
AI summary
A system including memory devices and a tester is provided. The tester is configured to: generate a first multi-purpose command to the memory devices and a first data signal to each of a first group in the memory devices to store a first identity; generate a second multi-purpose command to the memory devices and the first data signal to each of a second group in the memory devices to store a second identity; generate a third multi-purpose command and a fourth multi-purpose command to the memory devices to select the first and second groups in the memory devices to have first and second time shifts in write leveling pulses therein separately; transmit a write datum to the memory devices for performing a write operation to the memory devices; and receive read data and compare the write datum and the read data for a test result.