Nonvolatile Memory Write Loop Adaptation

Solution Overview

Problem

Flash memory devices experience reduced threshold voltage over time due to charge discharge, leading to increased write loops and potential write errors, especially when mixing cycled and fresh cells in the same memory cell array.

Innovation Solution

The solution involves adjusting the verify voltage and program voltage based on the number of write loops, allowing for easier verify operation pass without compromising retention characteristics, by using a higher verify voltage for cycled cells and a lower verify voltage for fresh cells, and modifying the program voltage step-up width accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the threshold voltage is programmed slightly higher in expectation of reduction due to long time leaving, then data retention is improved, but the number of write loops increases and write errors occur

Engineering Contradiction:

Improvedata retentionVSAvoidnumber of write loops

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the verify voltage parameter dynamically based on the number of write loops. For fresh memory cells (write loops ≤ threshold), a first verify voltage is used, and for cycled memory cells (write loops > threshold), a second verify voltage is used. This parameter change allows the system to adapt to different cell states and prevents excessive write loops while maintaining data retention.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic verification by switching between different verify voltages based on the write loop count. This dynamic approach allows the verification condition to adapt to the memory cell's wear state, preventing the system from using a fixed verify voltage that would cause excessive write loops for fresh cells while maintaining reliability for cycled cells.

Inventive Principle:

Principle #15Dynamics

2Reliability

If the verify voltage is increased to ensure verify-pass, then write reliability is improved, but fresh cells cannot complete programming due to excessive write loops

Engineering Contradiction:

Improveverify-pass reliabilityVSAvoidprogramming completion rate

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent changes the verify voltage parameter based on the memory cell's write loop history. By using a lower first verify voltage for fresh cells and a higher second verify voltage for cycled cells, the system ensures that fresh cells can complete programming while cycled cells maintain reliable verification.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies different verify voltages to different groups of memory cells based on their wear state. Fresh cells (with fewer write loops) use a first verify voltage, while cycled cells (with more write loops) use a second verify voltage. This local differentiation allows each cell group to be verified under optimal conditions.

Inventive Principle:

Principle #3Local quality

3Device complexity

If the same write conditions are used for all memory cells, then device complexity is reduced, but write failures occur in fresh cells while maintaining cycled cells

Engineering Contradiction:

Improvewrite condition uniformityVSAvoidwrite success rate

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent applies different verify voltages to different groups of memory cells based on their wear state. Fresh cells (with fewer write loops) use a first verify voltage, while cycled cells (with more write loops) use a second verify voltage. This local differentiation allows each cell group to be verified under optimal conditions, improving overall write success rate.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent introduces dynamic verification by switching between different verify voltages based on the write loop count. This dynamic approach allows the verification condition to adapt to the memory cell's wear state, preventing the system from using a fixed verify voltage that would cause excessive write loops for fresh cells while maintaining reliability for cycled cells.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8811089B2Nonvolatile semiconductor memory device

Publication Date: 2014.08.19 KIOXIA CORP

AI summary

A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural memory cells operative to store data nonvolatilely in accordance with plural different threshold voltages; and a control unit operative to, in data write to the memory cell, execute write loops having a program operation for changing the threshold voltage of the memory cell and a verify operation for detecting the threshold voltage of the memory cell after the program operation, the control unit, in data write for changing one threshold voltage of the plural threshold voltages, executing the verify operation, when the number of write loops to the memory cell becomes more than a certain defined number, using a condition that can pass the verify operation easier than that when the number of write loops is equal to or less than the certain defined number.