Semiconductor Memory Write Loop Verification Optimization
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Solution Overview
Problem
In nonvolatile semiconductor memory devices, the cell-to-cell interference effect leads to a widened threshold distribution of memory cells, making it difficult to maintain a narrow threshold range required for multi-level cells, which in turn prolongs the write time.
Innovation Solution
A semiconductor memory device with a write sequence that includes multiple write loops and verify operations, where the controller determines the (n+k)-th verify operation based on the comparison between the n-th and (n+1)-th verify operations, allowing for a verify-skip operation to optimize the write process and reduce write time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the threshold distribution of the memory cell is narrowed to accommodate multi-level cell values, then the manufacturing precision is improved, but the write time is lengthened due to the cell-to-cell interference effect
Solution Approach 1:
The write operation is divided into multiple write loops, each consisting of a write operation followed by a verify operation. This segmentation allows the system to write data in controlled stages and verify the threshold voltage distribution after each stage, enabling precise control over the threshold distribution while managing write time through iterative refinement rather than prolonged continuous writing.
Solution Approach 2:
The verify operation reads the threshold voltage distribution after each write loop and provides feedback to the controller. Based on this feedback, the controller determines whether to continue with additional write loops or skip ahead, allowing dynamic adjustment of the write process to achieve the desired threshold distribution precision while minimizing unnecessary write time.
2Reliability
If multiple verify operations are performed to ensure accurate threshold voltage distribution, then the reliability is improved, but the write time is extended
Solution Approach 1:
The number of verify operations performed is made dynamic rather than fixed. The controller adjusts the number of verify operations based on the actual threshold voltage distribution measured in previous verify operations. When the distribution is already within acceptable ranges, the controller can reduce or skip subsequent verify operations, maintaining reliability while adapting write time to actual conditions.
Solution Approach 2:
The verify operation parameters, specifically the verify voltage levels and the number of verify loops, are adjusted based on the progression of the write process. As the threshold distribution converges toward the target values, the verify parameters can be modified to reduce the number of required verify operations, thereby maintaining reliability while reducing the time spent on verification.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit.The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.