Memory Write Deserializer Layout for Time-Aligned Data Masking
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining high-speed operations while performing data masking operations, as timing alignment of mask patterns with data can be difficult to achieve, leading to reduced effective write cycles and compromised operation speed.
Innovation Solution
The implementation of a semiconductor device with a first deserializer and a second deserializer, both configured to have matching timing characteristics, allows for time-aligned mask patterns and parallel data. This is achieved through a circuit structure that includes sampling, shift, and output stages, with the clock generator producing write clock signals that synchronize the deserialization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data masking operation is performed in high speed memory device, then data writing capability is improved, but timing alignment between mask pattern and parallel data becomes difficult to achieve
Solution Approach 1:
The patent divides the data stream into multiple parallel data streams and applies separate mask patterns to each stream. This segmentation allows independent timing control for each parallel stream, making it easier to achieve precise timing alignment between mask patterns and data without compromising overall writing capability
Solution Approach 2:
The patent generates multiple copies of the mask pattern, one for each parallel data stream. Each mask pattern copy is synchronized with its corresponding parallel data stream, ensuring timing alignment is maintained across all streams while preserving full data writing capability
2Productivity
If mask pattern timing alignment is achieved, then effective write cycle is enhanced, but device complexity increases
Solution Approach 1:
The patent designs the deserializer to perform multiple functions: it simultaneously deserializes incoming data into parallel streams and generates the required mask patterns. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while still achieving timing alignment to enhance effective write cycle
3Speed
If high speed operation is maintained, then operation speed is preserved, but timing alignment of mask pattern becomes compromised
Solution Approach 1:
The patent performs preliminary deserialization and mask pattern generation within the deserializer before the data and mask patterns are combined. This preliminary action ensures that timing alignment is established early in the data path, allowing high-speed operation to be maintained without compromising the precision of mask pattern timing alignment
Data Source
AI summary
A semiconductor device includes a first deserializer, a second deserializer, a write data converter coupled to the first deserializer and the second deserializer, and a clock generator coupled to the first deserializer and the second deserializer. The first deserializer is configured to convert serial data to parallel data with a first timing alignment based on a set of write clock signals. The second deserializer is configured to output a mask pattern with a second timing alignment based on the set of write clock signals. The first deserializer and the second deserializer are configured to have a same circuit structure. The write data converter is configured to output valid data based on the parallel data and the mask pattern. The clock generator is configured to output the set of write clock signals.