Nonvolatile Memory Write Mode Switching for Capacity and Endurance
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Solution Overview
Problem
Nonvolatile memory systems face limitations due to the finite number of program/erase cycles and increased memory density leading to reduced write and read times, with existing systems failing to efficiently manage data storage and performance across different write modes.
Innovation Solution
A memory system that dynamically switches between write modes based on the number of bits stored per memory cell, using a controller to adaptively select between SLC, MLC, TLC, and QLC modes to optimize storage capacity and performance based on utilization thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored per memory cell increases (MLC, TLC, QLC modes), then storage capacity increases, but write and read speeds become longer and performance decreases
Solution Approach 1:
The system dynamically switches between different write modes (SLC, MLC, TLC, QLC) based on current operational conditions such as wear-out degree and utilization rate. This allows the memory system to adapt its storage capacity and performance characteristics in real-time, selecting SLC mode for high-speed operations and MLC/TLC/QLC modes for high-capacity operations as needed
Solution Approach 2:
The invention changes the operational parameters of the memory cells by adjusting the number of bits stored per cell based on wear-out degree and utilization rate. By modifying this parameter dynamically, the system can optimize between storage capacity and access speed according to current system state
2Productivity
If the number of program/erase cycles exceeds the limited number, then storage operations increase, but the nonvolatile memory fails and reliability decreases
Solution Approach 1:
The system dynamically adjusts the write mode based on the wear-out degree of memory blocks, switching to more robust modes (SLC) when wear-out degree is high to reduce further degradation, and allowing more aggressive usage when wear-out degree is low. This dynamic adaptation extends the overall lifespan of the memory system
Solution Approach 2:
The system continuously monitors the wear-out degree of memory blocks and uses this feedback information to make real-time decisions about write mode selection. This closed-loop control ensures that operational patterns are adjusted based on actual memory health status, preventing catastrophic failure
3Productivity
If SLC mode is used to improve write and read performance, then storage capacity decreases due to fewer bits per cell
Solution Approach 1:
The system dynamically selects between SLC mode (high performance, lower capacity) and multi-level cell modes (lower performance, higher capacity) based on current utilization rate and wear-out degree. This allows the system to maximize storage capacity during normal operation while switching to SLC mode when performance is critical or when utilization is low
Solution Approach 2:
The invention changes the bits-per-cell parameter dynamically based on system conditions. By adjusting this parameter between 1 bit (SLC) and multiple bits (MLC/TLC/QLC) per cell, the system can optimize the trade-off between storage capacity and access performance according to current needs
4Quantity of substance
If multi-level cell mode is used to increase storage capacity, then the time required to write and read data increases
Solution Approach 1:
The system dynamically adjusts the write mode based on utilization rate, switching between high-capacity modes (MLC, TLC, QLC) and high-speed mode (SLC) to optimize the balance between storage capacity utilization and access time. This prevents excessive access times when capacity is not fully utilized
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.