Memory Write Parameter Adjustment for Endurance

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Solution Overview

Problem

Non-volatile memory devices, such as phase change memory, suffer from limited write endurance and retention due to physical degradation from repeated access, leading to decreased performance over time.

Innovation Solution

A mechanism to track the age of the memory device through write operations and adjust write parameters, such as voltages and pulse shapes, based on defined bins of write operations to mitigate degradation and improve write success rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write operations are performed repeatedly to store data in non-volatile memory devices, then data storage capability is achieved, but physical degradation occurs leading to limited write endurance and retention

Engineering Contradiction:
Improvewrite enduranceVSAvoiddevice lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies dynamics by making write parameters adjustable and adaptive rather than fixed. The control logic dynamically modifies write parameters (such as pulse amplitude, duration, or shape) based on the determined age of the memory device, allowing the system to optimize write operations for different stages of device aging and thereby extend write endurance

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent directly applies parameter changes by modifying write parameters based on the determined age of the memory device. The control logic adjusts specific parameters (voltage levels, pulse timing, waveform characteristics) according to age thresholds, which compensates for physical degradation and maintains reliable write operations over extended periods

Inventive Principle:
Principle #35Parameter changes

2Reliability

If write parameters are adjusted based on device age to extend lifespan, then write success rate is improved, but device complexity increases due to age tracking and parameter adjustment mechanisms

Engineering Contradiction:
Improvewrite success rateVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by enabling the memory device to automatically track its own age and adjust write parameters without external intervention. The control logic within the device determines age based on internal state (such as write count or retention characteristics) and autonomously selects appropriate write parameters, eliminating the need for complex external monitoring systems

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements feedback by using the determined age of the memory device to inform and adjust subsequent write operations. The control logic continuously monitors device state, determines age, and uses this information to adapt write parameters, creating a closed-loop system that improves write success rate while keeping the control mechanism relatively simple

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively extends the lifespan of memory devices by adjusting write parameters according to the device's age, reducing the likelihood of failed operations and maintaining data storage reliability.

Implementation Method 1

determining an age of the memory device based on a number of write operations performed by the memory device

Methodology Applied
Scientific EffectWrite count tracking:

Data Source

PatentEP3368990B1Apparatuses and methods for adjusting write parameters based on a write count
Publication Date: 2022.02.23 MICRON TECHNOLOGY INC
  • EP3368990B1 patent drawingFigure 1A
  • EP3368990B1 patent drawingFigure 1B
  • EP3368990B1 patent drawingFigure 2

AI summary

According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.