Memory Write Distribution With Parity Location Encoding
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Solution Overview
Problem
Existing data processing systems face challenges in efficiently storing and retrieving data from memory devices while ensuring data safety and reliability, particularly in handling large volumes of data and correcting errors.
Innovation Solution
A memory system is designed to distribute write data across multiple regions, utilizing parity generating circuitry to perform logical operations on data entries and generate parity entries, enhancing data reliability and reducing operational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is distributed and stored in plural regions of the memory device, then data safety is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple memory regions (first memory region, second memory region, third memory region) where data is distributed and stored in segments. This segmentation approach improves data safety by isolating data across regions while managing complexity through structured organization of data blocks and parity information in each region.
2Reliability
If write data is distributed across multiple memory regions, then data reliability is improved, but operational complexity increases
Solution Approach 1:
The memory system performs self-service through automatic parity generation and error correction. The controller automatically generates parity data from distributed write data and stores it in the memory regions, and automatically corrects errors during read operations without requiring external intervention, thereby improving reliability while maintaining ease of operation.
3Reliability
If parity generating circuitry is used to perform logical operations on data entries, then error correction capability is improved, but resource usage increases
Solution Approach 1:
The system changes parameters by dynamically adjusting the amount of parity data generated and stored based on the specific data distribution pattern and error correction requirements. By optimizing the parity generation parameters, the system achieves adequate error correction capability while minimizing the quantity of resources (memory space, processing power) consumed for parity operations.
Data Source
AI summary
A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.