Memory Write Distribution With Parity Mapping Across Regions
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Solution Overview
Problem
Existing memory systems face challenges in efficiently distributing and storing data across multiple regions to enhance data safety and reliability while minimizing operational complexity and performance degradation.
Innovation Solution
A memory system apparatus and method that distributes write data across plural regions, utilizing parity generating circuitry to perform logical operations on data entries, generating parity entries, and managing these entries with a flash translation layer to improve reliability and reduce resource overheads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is distributed and stored in plural regions of the memory device, then data safety and reliability are improved, but operational complexity increases
Solution Approach 1:
The memory device is divided into multiple memory regions (first memory region, second memory region, third memory region) where data is segmented and distributed across these regions. Each region stores specific data entries, and the system manages these segmented regions independently to achieve both reliability through distribution and manageable complexity through structured organization.
2Reliability
If data is distributed and stored in plural regions of the memory device, then data safety and reliability are improved, but performance degradation occurs
Solution Approach 1:
The system performs preliminary actions by pre-establishing the distribution pattern of data across memory regions and pre-organizing data entries before actual storage operations. The flash translation layer pre-processes write commands to determine optimal placement in different memory regions, reducing the complexity and time of actual data distribution operations.
Solution Approach 2:
The flash translation layer acts as an intermediary between the host system and the physical memory regions. It translates high-level write commands into region-specific operations, managing the complexity of distributed storage transparently and improving performance by optimizing data placement strategies without requiring application-level awareness of the distributed architecture.
3Reliability
If parity generating circuitry is used to perform logical operations on data entries, then data reliability is improved, but resource overheads increase
Solution Approach 1:
The parity generating circuitry is merged with the existing memory control logic and flash translation layer, allowing parity generation to occur alongside normal data operations. This integration reduces the need for separate dedicated hardware resources while maintaining the reliability benefits of parity generation through logical operations on data entries.
Data Source
AI summary
A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.