Memory Write Queue Handling to Reduce Write Amplification

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Solution Overview

Problem

Conventional memory systems experience increased write amplification and reduced data performance due to the loss of sequentiality in data access requests caused by multicore hardware processors, leading to inefficient garbage collection operations.

Innovation Solution

Process write requests on a memory system based on queue identifiers associated with the requests, using an inline approach to park and coalesce sequential write requests and an offline approach to organize data migration during garbage collection based on common queue identifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data access requests are processed using conventional memory systems with multicore hardware processors, then processing capacity is increased, but sequentiality of data access requests is lost leading to increased write amplification and reduced data performance

Engineering Contradiction:
Improveprocessing capacityVSAvoidwrite amplification
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments data access requests by assigning each request a queue identifier (QID) that corresponds to a specific submission queue. This segmentation preserves the sequentiality characteristics of each queue while allowing parallel processing across multiple queues, thus maintaining processing capacity while reducing write amplification caused by random access patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary classification of data access requests by assigning queue identifiers before processing. By pre-organizing requests into sequential queues based on QID, the system prepares data in an optimal order for memory operations, preventing the loss of sequentiality that would otherwise occur during parallel multicore processing.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If conventional memory systems process write requests without queue identifier-based organization, then processing simplicity is maintained, but garbage collection operations become inefficient with higher overhead

Engineering Contradiction:
Improveprocessing simplicityVSAvoidgarbage collection overhead
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments data during garbage collection operations by organizing data migration according to queue identifiers. This segmentation allows the garbage collection process to handle data in organized batches associated with specific QIDs, improving efficiency without significantly increasing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the organization parameter of data storage by incorporating queue identifier information into the data structure. This parameter change enables the garbage collection process to efficiently identify and migrate data based on QID, reducing overhead while maintaining relatively simple processing logic.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If multicore hardware processors handle data access requests simultaneously, then throughput is improved, but sequentiality of requests is lost resulting in reduced data performance

Engineering Contradiction:
ImprovethroughputVSAvoiddata performance degradation
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the data access request stream into multiple independent queues identified by QID. Each queue maintains its own sequentiality characteristics, allowing simultaneous processing of multiple queues by different cores while preserving the sequential access patterns within each queue, thus improving throughput without sacrificing data performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The queue identifier acts as an intermediary that bridges the parallel processing capability of multicore processors with the sequentiality requirements of data access. By routing requests through QID-based submission queues, the system enables parallel processing while maintaining sequential access patterns through the intermediary queue structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12468465B2Processing write requests based on queue identifier
Publication Date: 2025.11.11 MICRON TECHNOLOGY INC
  • US12468465B2 patent drawing
  • US12468465B2 patent drawing
  • US12468465B2 patent drawing

AI summary

Various embodiments provide for processing write requests on a memory system based on queue identifiers associated with the write requests. In particular, input data streams can be received and stored by submission queues of a memory system, and write requests in the input data streams can be separated and processed based on queue identifiers associated with the submission queues using an inline approach for writing data on the memory system, an offline approach for writing data on the memory system, or both.