Memory Write Circuit Segmentation for Lower RC Loading
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Solution Overview
Problem
High-speed memory devices face issues with signal distortion and increased resistance-capacitance (RC) loading due to memory banks being driven by a single pair of write data wirings, leading to failed write procedures, especially for banks farther from the global write circuit.
Innovation Solution
The memory device divides memory banks into groups, using separate pairs of write data wirings for different groups to reduce RC loading, with each group having its own pair of global write signals and complement signals, thereby optimizing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single pair of write data wirings is used to drive all memory banks, then the device complexity is reduced, but the RC loading increases and signal distortion occurs
Solution Approach 1:
The memory banks are divided into multiple groups, with each group driven by a dedicated pair of write data wirings. This segmentation reduces the RC loading on each wiring pair while maintaining manageable device complexity through systematic organization.
2Productivity
If separate pairs of write data wirings are used for different memory bank groups, then the RC loading is reduced and writing speed is enhanced, but the device complexity increases
Solution Approach 1:
Memory banks are segmented into groups that can be driven independently by separate write data wiring pairs, enabling parallel write operations and reducing RC loading effects while maintaining organized device structure.
Solution Approach 2:
The write circuit structure is made dynamic by enabling selective activation of different write data wiring pairs based on which memory bank group is being accessed, allowing the system to adapt its complexity to actual operational needs.
3Device complexity
If memory banks farther from the global write circuit are driven by the same write data wirings, then the device complexity is reduced, but signal distortion increases and write operations fail
Solution Approach 1:
Memory banks are segmented into proximity-based groups, with each group assigned its own write data wiring pair. This ensures that banks at similar distances from the global write circuit are driven together, minimizing signal distortion while maintaining systematic device organization.
Data Source
AI summary
A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.